參數(shù)資料
型號(hào)： TPS54550PWPRG4
廠商： TEXAS INSTRUMENTS INC
元件分類(lèi)： 穩(wěn)壓器
英文描述： 9.5 A SWITCHING REGULATOR, 700 kHz SWITCHING FREQ-MAX, PDSO16
封裝： GREEN, PLASTIC, HTSSOP-16
文件頁(yè)數(shù)： 8/31頁(yè)
文件大小： 913K
代理商： TPS54550PWPRG4
www.ti.com
APPLICATION INFORMATION
AGND
BOOT
VSENSE
COMP
PWRGD
PH
3.3OR5V
VBIAS
RT
SYNC
SS/ENA
LSG
UVLO
VIN
PGND
VOUT
PH
Vin
TOPSIDEGROUND AREA
VIA
ANALOGGROUND TRACE
EXPOSED
POWERPAD
AREA
OUTPUT INDUCTOR
OUTPUT
FILTER
CAPACITOR
BOOT
CAPACITOR
AND
RESISTOR
INPUT
BYPASS
CAPACITOR
INPUT
BULK
FILTER
FREQUENCY
SET
RESIST
OR
SLOWSTART
CAPACITOR
BIAS
CAPACITOR
LOW
SIDE
FET
TERMINA
TIONRES.(10K)
UNDERVOLTAGE
LOCKOUT
RESISTORDIVIDER
POWERGOODPULLUP
COMPENSATIONNETWORK
BACKSIDEorINTERNAL
LAYER TRACE
PCB LAYOUT
SLVS623A – MARCH 2006 – REVISED APRIL 2006
Figure 26. TPS54550 PCB Layout
conductor minimized to prevent excessive capacitive
coupling. The recommended conductor width from
pins 14 and 15 is 0.050 inch to 0.075 inch of 1-ounce
The VIN pins should be connected together on the
to 2-ounce copper. The length of the copper land
printed circuit board (PCB) and bypassed with a low
pattern should be no more than 0.2 inch.
ESR ceramic bypass capacitor. Care should be
For operation at full rated load, the analog ground
taken to minimize the loop area formed by the
plane must provide adequate heat dissipating area.
bypass capacitor connections, the VIN pins, and
A 3-inch by 3-inch plane of copper is recommended,
source of the low-side MOSFET. The minimum
though
not
mandatory,
depending
on
ambient
recommended bypass capacitance is 10-
μF ceramic
temperature and airflow. Most applications have
with a X5R or X7R dielectric and the optimum
larger areas of internal ground plane available, and
placement is closest to the VIN pins and the source
the PowerPAD should be connected to the largest
of the low-side MOSFET. See Figure 26 for a PCB
area available. Additional areas on the bottom or top
layout example. The AGND and PGND pins should
layers also help dissipate heat, and any area
be tied to the PCB ground plane at the pins of the IC.
available should be used when 5 A or greater
The source of the low-side MOSFET should be
operation is desired. Connection from the exposed
connected directly to the PCB ground plane. The PH
area of the PowerPAD to the analog ground plane
pins should be tied together and routed to the drain
layer should be made using 0.013-inch diameter vias
of the low-side MOSFET. Since the PH connection is
to avoid solder wicking through the vias. Four vias
the switching node, the MOSFET should be located
should be in the PowerPAD area with four additional
very close to the PH pins, and the area of the PCB
vias outside the pad area and underneath the
package.
Additional
vias
beyond
those
recommended
to
enhance
thermal
performance
should be included in areas not under the device
package. See Figure 27.
16
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