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參數(shù)資料
| 型號： | TPS54550PWPRG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | 9.5 A SWITCHING REGULATOR, 700 kHz SWITCHING FREQ-MAX, PDSO16 |
| 封裝： | GREEN, PLASTIC, HTSSOP-16 |
| 文件頁數(shù)： | 2/31頁 |
| 文件大?。?/td> | 913K |
| 代理商： | TPS54550PWPRG4 |
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Internal Oscillator
VO(PH)
VO(SYNC)
Power Good (PWRGD)
Bootstrap Voltage (BOOT)
Error Amplifier
Voltage Reference
T
delay +
1000
s(kHz)
ms
(5)
Bias Voltage (VBIAS)
SLVS623A – MARCH 2006 – REVISED APRIL 2006
Figure 4. SYNC Output Waveform
Up to 1 mA of current can be drawn for use in an
external application circuit. The VBIAS pin must have
a bypass capacitor value of 1.0
μF. X7R or X5R
The VSENSE pin is compared to an internal
grade
dielectric
ceramic
capacitors
are
reference signal. If the VSENSE is greater than 97%
recommended because of the stable characteristics
and no other faults are present, the PWRGD pin
over temperature.
presents a high impedance. A low on the PWRGD
pin indicates a fault. The PWRGD pin has been
designed to provide a weak pull-down and indicates
a fault even when the device is unpowered. If the
The BOOT capacitor obtains its charge cycle by
TPS54550 has power and has any fault flag set, the
cycle from the VBIAS capacitor. A capacitor and
TPS54550 indicates the power is not good by driving
small value resistor from the BOOT pin to the PH
the PWRGD pin low. The following events, alone or
pins are required for operation. The bootstrap
in combination, indicate power is not good:
connection for the high-side driver must have a
bypass capacitor of 0.1
μF and 24-
resistor .
VSENSE pin out of bounds
Overcurrent
Thermal shutdown
The VSENSE pin is the error amplifier inverting input.
UVLO undervoltage
The error amplifier is a true voltage amplifier with 1.5
Input voltage not present (weak pull-down)
mA of drive capability with a minimum of 60 dB of
Slow-starting
open-loop voltage gain and a unity gain bandwidth of
VBIAS voltage is low
2 MHz.
Once the PWRGD pin presents a high impedance
(i.e., power is good), a VSENSE pin out of bounds
condition forces PWRGD pin low (i.e., power is bad)
The voltage reference system produces a precision
after a time delay. This time delay is a function of the
reference
signal
by
scaling
the
output
of
a
switching
frequency
and
is
calculated
using
temperature
stable
bandgap
circuit.
During
production testing, the bandgap and scaling circuits
are trimmed to produce 0.891 V at the output of the
error amplifier, with the amplifier connected as a
voltage follower. The trim procedure improves the
regulation, since it cancels offset errors in the scaling
and error amplifier circuits.
The VBIAS regulator provides a stable supply for the
internal analog circuits and the low-side gate driver.
10
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