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參數(shù)資料
| 型號： | TPS54362QPWPRQ1 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | 8 A SWITCHING REGULATOR, 2200 kHz SWITCHING FREQ-MAX, PDSO20 |
| 封裝： | GREEN, PLASTIC, HTSSOP-20 |
| 文件頁數(shù)： | 5/34頁 |
| 文件大?。?/td> | 826K |
| 代理商： | TPS54362QPWPRQ1 |
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www.ti.com
SLVS845C – MARCH 2009 – REVISED MAY 2010
The internal reference voltage has a ±1.5% tolerance. The overall output voltage tolerance will be dependent on
the external feedback resistors. To determine the overall output voltage tolerance, use the following relationship:
tolVReg = tolVref + (R4/(R4 + R5)) × (tolR4 + tolR5)
(2)
Where R4 and R5 are feedback resistors.
Vref = 0.8V (typical)
The VReg pin is also internally connected to a load of 100
Ω, which is turned ON in the following conditions:
During startup conditions, when the device is powered up with no-load, or whenever EN is toggled, the
internal load connected to VReg pin is turned ON for about 100 s to charge the bootstrap capacitor to
provide gate drive voltage to the switching transistor.
During normal operating conditions, when the regulated output voltage exceeds the overvoltage threshold
(preset by external resisitors R1, R2, and R3), the internal load is turned ON, and this pin is pulled down to
bring the regulated output voltage down.
Typically an output capacitor within the range of 10-400mF is used. This terminal will have a filter capacitor with
low ESR characteristics in order to minimize output ripple voltage.
OSCILLATOR FREQUENCY: (RT)
Oscillator frequency is selectable by means of a resistor placed at the RT pin. The switching frequency (Fsw) can
be set in the range 200 kHz – 2200 kHz. In addition, the switching frequency can be imposed externally by a
clock signal (Fext) at the SYNC pin with Fsw < Fext< 2×Fsw. In this case the external clock overrides the
switching frequency determined by the RT pin and the internal oscillator is clocked by the external
synchronization clock.
Figure 13. Switching Frequency vs Resistor Value
SYNCHRONIZATION (SYNC)
This is an external input signal to synchronize the switching frequency using an external clock signal. The
synchronization input will over-ride the internally fixed oscillator signal. The synchronization signal has to be valid
for approximately 2 clock cycles (pulses) before the transition is made for synchronization with the external
frequency input. If the external clock input does NOT transition low or high for 32mS (typ), the system will default
to the internal clock set by the RT pin. The SYNC input clock can have a maximum frequency of 2X the
programmed clock frequency up to a maximum value of 2.2MHz
Copyright 2009–2010, Texas Instruments Incorporated
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Product Folder Link(s) :TPS54362-Q1
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