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參數(shù)資料
| 型號： | TPS54362QPWPRQ1 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | 8 A SWITCHING REGULATOR, 2200 kHz SWITCHING FREQ-MAX, PDSO20 |
| 封裝： | GREEN, PLASTIC, HTSSOP-20 |
| 文件頁數(shù)： | 4/34頁 |
| 文件大?。?/td> | 826K |
| 代理商： | TPS54362QPWPRQ1 |
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SLVS845C – MARCH 2009 – REVISED MAY 2010
www.ti.com
OVERVIEW
The TPS54362 is a 60V, 3A dc/dc step down (buck) converter using voltage-control mode scheme. The device
features supervisory function for power-on-rest during system power on. Once the output voltage has exceeded
the threshold set by RST_TH, a delay of 1ms/nF (based on capacitor value on RSTDLY terminal) is invoked
before RST line is released high. Conversely on power down, once the output voltage falls below the same set
threshold, the RST is pulled low only after a de-glitch filter of approximately 20ms (typ) expires. This is
implemented to prevent RST from being triggered due to fast transient line noise on the output supply.
An overvoltage monitor function, is used to limit output voltage to the threshold set by OV_TH. Both the RST_TH
and OV_TH monitoring voltages are set to be a pre-scale of the output voltage, and thresholds based on the
internal bias voltages of the voltage comparators (0.8V typical).
Detection of undervoltage on the output is based on the RST_TH setting and will invoke RST line to be asserted
low. Detection of over-voltage on the output is based on the OV_TH setting and will NOT invoke the RST line to
be asserted low. However, the internal switch is commanded to turn OFF.
In systems where power consumption is critical, low power mode is implemented to reduce the non-switching
quiescent current during light load conditions. The PFM operation is determined when the system enters
discontinuous current mode (DCM) for at least 100ms. The operation of when the device enters discontinuous
mode is dependent on the selection of external components.
If thermal shutdown is invoked due to excessive power dissipation, the internal switch is disabled and the
regulated output voltage will start to decrease. Depending on the load line the regulated voltage could decay and
the RST_TH threshold may assert the RST output low.
DETAILED DESCRIPTION
The TPS54362 is a DC/DC Converter using a voltage-control mode scheme with an input voltage feed-forward
technique. The device can be programmed for a range of output voltages with a wide input voltage range. Below
are details with regard to the pin functionality.
INPUT VOLTAGE
The VIN pin is the input power source for the TPS54362. This pin must be externally protected against voltage
level greater than 60V and reverse battery. In Buck Mode the input current drawn from this pin is pulsed, with
fast rise and fall times. Therefore, this input line requires a filter capacitor to minimize noise. Additionally, for EMI
considerations, an input filter inductor may also be required.
FUNCTION MODE
OPERATING VOLTAGE
FUNCTION
OUTPUT CURRENT CAPABILITY
COMMENTS
RANGE
Optimum performance: VIN/VReg ratios
VReg = 0.9V to 18V and ILoad Up to 3A;
should always be set such that min required
Buck
3.6V to 48V
however, at higher output power the part
duty cycle pulse (ton min) >150ns. The min off
is derated for max temperature rating
time is 250ns for ALL conditions.
OUTPUT VOLTAGE VReg
The output voltage VReg is generated by the converter supplied from the battery voltage VIN and the external
components (L, C). The output is sensed through an external resistor divider and compared with an internal
reference voltage.
The value of the adjustable output voltage in Buck Mode is selectable between 0.9V and 18V by choosing the
external resistors, according to the relationship:
VReg = Vref (1 + R4/R5)
(1)
Where R5 and R4 are feedback resistors.
Vref = 0.8V (typical)
12
Copyright 2009–2010, Texas Instruments Incorporated
Product Folder Link(s) :TPS54362-Q1
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