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參數(shù)資料
| 型號： | TPS51120RHBRG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | 0.1 A DUAL SWITCHING CONTROLLER, 350 kHz SWITCHING FREQ-MAX, PQCC32 |
| 封裝： | GREEN, PLASTIC, QFN-32 |
| 文件頁數(shù)： | 8/39頁 |
| 文件大小： | 826K |
| 代理商： | TPS51120RHBRG4 |
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Undervoltage Protection
5V Supply and UVLO Protection
VIN Line Sag protection (Dynamic UVP)
Thermal Shutdown
SLUS670B – JULY 2005 – REVISED FEBRUARY 2007
DETAILED DESCRIPTION (continued)
For under voltage protection (UVP), the TPS51120 monitors VFB voltage. When the VFB voltage is lower than
70% of the target and the UVP comparator output goes high, the internal UVP delay counter begins count. After
the 128 clocks, approximately 0.5 ms, TPS51120 latches off both channels as DRVH and DRVL at low. This
function is enabled after the softstart reference has exceeded the internal 1-V reference operation to ensure
startup. Please refer to Table 5.
TPS51120 has two 5-V terminals. VREG5 is the output of 5-V linear regulator. This terminal also serves as input
pin for the gate driver circuits. Internal switchover FET is connected between this pin and VO1. V5FILT is the
VCC supply input for the control circuitry on the chip. Connect with R-C low pass filter from VREG5 to this
V5FILT to eliminate spiky high frequency noise. State definition pins such as SKIPSEL, TONSEL, VFB (fixed
output case) and COMP (for D-CAP mode) or CS resistors that need stable 5V should refer to V5FILT. The part
has 5-V supply under voltage lock out protection (UVLO) to prevent unpredictable operation under insufficient
power. The TPS51120 monitors VREG5 voltage. When the VREG5 voltage is lower than UVLO threshold, the
SMPS’s are shut off. The output discharge or ‘soft stop’ feature is enabled for the channel one and channel two.
However, because the discharge circuit derives its power from the 5-V line, power must be presented long
enough to ensure that discharge is complete during shutdown. Also, during power up, the TPS51120 attempts to
discharge the output capacitor until the UVLO (on) threshold is reached. A 5-V UVLO is non-latch protection and
is automatically resumed up on 5-V recovery.
Since the TPS51120 serves primarily as system power (i.e. used for generating 3.3 V and 5 V) it is very
important that the system not enter UVP if the VIN supply has dropped below 6V. UVP would be caused by the
5-V output dropping due to input line sag. When the VIN pin drops below the 5-V regulator voltage, the 5-V
regulator ‘tracks’ VIN (LDO operation). The UVP threshold is adjusted downward when the VREG5 is below
4.8 V. This ensures that 5-V supply UVLO trips before the latching UVP condition occurs and the system power
can recover normally when VIN recovers. This feature is very useful for transient VIN events such as adapter
insertion
The TPS51120 employs thermal shutdown for the switchers at 145
°C. This is a non-latch protection with
hysteresis of 10
°C. Both switching regulators and both internal regulators stop. VREG5 and VREG3 LDOs may
not turn on if the part is preheated above the recovery temperature before starting up. Reduce the temperature
to or below TA = 85°C to resume operation safely.
Table 4. Enable Logic States (VOUT1=5 V, VOUT2=3.3 V)
EN5(1)
EN3
EN1
EN2
VREG5
VREG3
VREF2(2)
SMPS1
SMPS2
Low
High or Low
Off
Low-to-High
Low
High or Low
LDO 5 V
Off
Low
Low-to-High
High or Low
Off
LDO 3.3 V
Off
Low-to-High
Low
LDO 5 V
LDO 3.3 V
On
Off
High
Low
Low-to-High
LDO 5 V
SW 3.3 V
On
Off
On
High
Low-to-High
Low
SW 5 V
LDO 3.3 V
On
Off
High
SW 5 V
SW 3.3 V
On
High-to-Low
High
SW 5 V
SW 3.3 V
On
High
High-to-Low
LDO 5 V
LDO 3.3 V
On
Off
High-to-Low
High
High-to-Low
High
Off
LDO 3.3 V
Off
High
High-to-Low
High
High-to-Low
SW 5 V
Off
On
Off
(1)
Because of Switch-over, the 5-V switcher MUST be turned off with the LDO in order to shut down the device. EN5 does NOT function as
a master DISABLE.
(2)
Forcing VREF2 output to ground disables SMPS1 and SMPS2 without latch.
16
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