參數(shù)資料
型號: TPS40055EVM
廠商: Texas Instruments, Inc.
英文描述: TPS40055 EVALUATION MODULE(TPS40055評估模塊)
中文描述: TPS40055評估模塊(TPS40055評估模塊)
文件頁數(shù): 9/18頁
文件大小: 350K
代理商: TPS40055EVM
SLUU190 April 2004
9
Wide Range Input TPS40055 Converter Delivers 5 Volts at 2 Amps
4.6
Output capacitor selection
Selection of the output capacitor is based on many application variables, including function, cost, size, and
availability. The minimum allowable output capacitance is determined by the amount of inductor ripple current
and the allowable output ripple, as given in equation (7)
C
OUT(min)
I
RIPPLE
f
8
V
RIPPLE
0.66 A
8
300 kHz
15 mV
18 F
In this design, C
OUT(min)
is 18-
μ
F with V
RIPPLE
= 15 mV. However, this only affects the capacitive component
of the ripple voltage, and the final value of capacitance is generally influenced by ESR and transient
considerations. To limit the voltage to 15 mV, the capacitor ESR should be less than equation (8),
R
C
V
RIPPLE
I
RIPPLE
15 mV
0.66 A
0.023 m
An additional consideration in the selection of the output inductor and capacitance value can be derived from
examining the transient voltage overshoot which can be initiated with a load step from full load to no load. By
equating the inductive energy with the capacitive energy the equation (9) can be derived:
C
O
L
I
2
V
2
L
I
OH
2
I
OL
2
V
f
2
V
I
2
22 H
(5.1 V)
2
(3 A)
2
(5.0 V)
2
196 F
where I
OH
= full load, I
OL
= no load, V
f
= allowed transient voltage rise, and V
I
= initial voltage. In this 3-A design
the capacitance required for limiting the transient is significantly larger than the capacitance required to keep
the ripple acceptably low. A single 330-
μ
F POSCAP capacitor C13 is installed in parallel with a 1-
μ
F ceramic
capacitor.
4.7
MOSFET selection
This wide range design required selection of a MOSFET capable of withstanding the maximum input voltage
of 40 V, and still capable of carrying the maximum load current of 3 A without overheating. This low cost design
uses a single SO-8 package which contains two MOSFETs, each rated for 55 V, and an R
DS(on)
of 55m
.
In a synchronous buck converter the fast-rising switch node voltage drives current through the drain-gate and
gate-source capacitance of the synchronous rectifier. This can raise the gate of the lower MOSFET to threshold
level even though the gate driver is attempting to hold the gate low.
[3]
C17 is added to the gate of Q1:B to increase
the capacitance ratio between the gate-source and drain-gate, reducing the voltage which appears on the lower
MOSFET gate.
(7)
(8)
(9)
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