參數(shù)資料
型號: TPS40055EVM
廠商: Texas Instruments, Inc.
英文描述: TPS40055 EVALUATION MODULE(TPS40055評估模塊)
中文描述: TPS40055評估模塊(TPS40055評估模塊)
文件頁數(shù): 8/18頁
文件大?。?/td> 350K
代理商: TPS40055EVM
SLUU190 April 2004
8
Wide Range Input TPS40055 Converter Delivers 5 Volts at 2 Amps
4.5
Input capacitor selection
The bulk input capacitor selection is based on several factors such as size, cost, and meeting voltage ripple
requirements. There are multiple configurations of various capacitor technologies that can function in the
application. In this example the goal is to achieve reduced overall cost in the solution provided.
The RMS current required by the power stage will be supplied by both the onboard capacitance and the input
source, with the relative impedances determining the magnitude of RMS current carried by each component.
In typical applications, this reference design would be fed from an upstream dc-to-dc converter with its own bulk
output capacitance, so the impedance presented to this converter could be rather low and less onboard
capacitance would be required. On the other hand, if conductors used to bring input power to this converter have
high series impedance then the onboard capacitors would be forced to carry more of the RMS ripple current,
and capacitors with higher current rating would be needed.
The maximum RMS current required for the buck power stage can be estimated as shown in equation (5),
I
I
OUT
D
I
OUT
V
OUT
V
IN
3
5
10
2.1 A
It is also important to consider a minimum capacitance value which would limit the voltage ripple to a specified
value if all the current is supplied by the onboard capacitor. For a typical ripple voltage of 150 mV the minimum
capacitance is calculated in equation (6) as:
C
I
t
V
I
V
O
V
V
IN
F
S
3.3 A
10 V
5 V
300 kHz
0.5 V
11 F
Initially, this design was fitted with a ceramic capacitor rated 10
μ
F, 50 V because some of the current would also
be supplied from the input source, limiting the voltage ripple to a value below the estimate. However, when
testing with a fast switch-on time there was voltage overshoot of 15 V to 20 V above the input source voltage.
This is a result of parasitic inductance in series with the input source interacting with the low-ESR ceramic
capacitor. To eliminate this issue the capacitor was changed to a 1.5-
μ
F, 50-V ceramic capacitor in parallel with
a 100-
μ
F aluminum electrolytic capacitor.
The 1.5-
μ
F ceramic capacitor C6 is positioned as a power bypass component located close to the MOSFET
packages to keep the high frequency current flow in a small, tight loop. The 100-
μ
F capacitor C11 has an ESR
of 0.35
, max which serves to dampen out the transient overshoot.
(5)
(6)
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