參數(shù)資料
型號： TPS3836H30DBVTG4
廠商： TEXAS INSTRUMENTS INC
元件分類： 電源管理
英文描述： 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO5
封裝： GREEN, PLASTIC, SOT-23, 5 PIN
文件頁數(shù)： 16/22頁
文件大小： 0K
代理商： TPS3836H30DBVTG4
Pull-up
50 A
V
TPS3836
TPS3837
TPS3838
www.ti.com
SLVS292E – JUNE 2000 – REVISED OCTOBER 2010
RECOMMENDED OPERATING CONDITIONS
MIN
MAX
UNIT
Supply voltage, VDD
1.6
6
V
Voltage range, CT, MR, RESET, and RESET pins
0
VDD + 0.3
V
High-level input voltage, VIH
0.7 × VDD
V
Low-level input voltage, VIL
0.3 × VDD
V
Input transition rise and fall rate at MR,
Δt/ΔV
100
ns/V
Operating temperature range, TA
–40
+85
°C
Pull-up resistor value, RESET pin (TPS3838 only)
Ω
ELECTRICAL CHARACTERISTICS
Over recommended operating conditions, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
RESET
VDD = 3.3 V, IOH = –2 mA
(TPS3836)
VDD = 6 V, IOH = –3 mA
VOH
High-level output voltage
0.8 × VDD
V
RESET
VDD = 1.8 V, IOH = –1 mA
(TPS3837)
VDD = 3.3 V, IOL = –2 mA
RESET
VDD = 1.8 V, IOL = 1 mA
(TPS3836,
VDD = 3.3 V, IOL = 2 mA
TPS3838)
VOL
Low-level output voltage
0.4
V
RESET
VDD = 3.3 V, IOL = 2 mA
(TPS3837)
VDD = 6 V, IOL = 3 mA
TPS3836,
VDD ≥ 1.1 V, IOL = 50 mA
0.2
V
TPS3838
Power-up reset voltage(1)
TPS3837
VDD ≥ 1.1 V, IOL = –50 mA
0.8 × VDD
V
TPS383xE18
1.66
1.71
1.74
TPS383xJ25
2.18
2.25
2.29
Negative-going input threshold
VIT
TPS383xH30
TA = –40°C to +85°C
2.70
2.79
2.85
V
voltage(2)
TPS383xL30
2.56
2.64
2.69
TPS383xK33
2.84
2.93
2.99
1.7 V < VIT < 2.5 V
30
VHYS
Hysteresis at VDD input
2.5 V < VIT < 3.5 V
40
mV
3.5 V < VIT < 5 V
50
MR (3)
MR = 0.7 × VDD, VDD = 6 V
–40
–60
–100
mA
IIH
High-level input current
CT
CT = VDD = 6 V
–25
+25
nA
MR (3)
MR = 0 V, VDD = 6 V
–130
–200
–340
mA
IIL
Low-level input current
CT
CT = 0 V, VDD = 6 V
–25
+25
nA
IOH
High-level output current
TPS3838
VDD = VIT + 0.2 V, VOH = VDD
25
nA
VDD > VIT, VDD < 3 V
220
400
nA
IDD
Supply current
VDD > VIT, VDD > 3 V
250
450
VDD < VIT
10
15
mA
Internal pull-up resistor at MR
30
k
CI
Input capacitance at MR and CT
VI = 0 V to VDD
5
pF
(1)
The lowest voltage at which the RESET output becomes active. tR, VDD ≥ 15 ms/V.
(2)
To ensure best stability of the threshold voltage, a bypass capacitor (ceramic, 0.1 mF) should be placed near the supply terminal.
(3)
If manual reset is unused, MR should be connected to VDD to minimize current consumption.
Copyright 2000–2010, Texas Instruments Incorporated
3
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