參數(shù)資料
型號: TPS2363PFBG4
廠商: TEXAS INSTRUMENTS INC
元件分類: 電源管理
英文描述: 1-CHANNEL POWER SUPPLY SUPPORT CKT, PQFP48
封裝: PLASTIC, TQFP-48
文件頁數(shù): 20/44頁
文件大小: 840K
代理商: TPS2363PFBG4
www.ti.com
SLUS680B – JANUARY 2006 – REVISED JANUARY 2010
Direct Mode
In direct mode, the TPS2363 is controlled by AUXENA/B to enable VAUXA/B and ONA/B to enable the main
supplies. FORCEONA/B can be used for test and debug. PGOODA/B and FAULTA/B is the only status available
without using the SMBus.
The SMBus does not have to be disabled to use direct mode. The SMBus can be used to read the status and
the general purpose inputs. Do not write to control A/B registers to when the TPS2363 is in direct mode. A write
to the control A/B registers switches the TPS2363 to SMBus mode. It will not switch back to direct mode until
power is cycled on the TPS2363. Writes to the function register are permitted to change the VAUXA/B current
limit and to disable the current limit.
If the SMBus is not used, pull SCL, SDA to 3.3 V or AUXINA/B with 100-k
resistors, A0 – A2 should be tied to
ground.
If the interrupt is not used, pull INT to 3.3 V or AUXINA/B with 100-k
resistors.
SMBus Mode
In SMBus mode, the TPS2363 is controlled by the SMBus Registers. Direct mode is disabled by connecting
AUXENA/B and ONA/B and tied to ground.
The FAULTA/B bit in the STATA/B register is an indication of the FAULTA/B pin and is inactive in SMBus mode.
Mode connections are summarized in the Power-On Reset section, MODE_PIN CONNECTION Table.
Programming
The clock and data line are pulled high with a 10-k
resistor to 3.3 V or AUXINA/B at the end of the SMBus. The
terminator sets to the default values on power up and when enabled.
The controller is programmed using the SDA and SCL pins, these are normally high, the falling edge of SCL
clocks the data. The sequence starts by asserting the data line, then at least 25 ns later asserting the clock.
Asserting is driving the line low. The clock should negate after 25 ns then the data should negate for a read or
stay asserted for a write. The clock asserts, then after 25 ns negates and the next clock assertion starts the read
or write with D7, D6, D5, D4, D3, D2, D1, D0, ACK (high), stop (low). The address is sent out with the
Read/Write bit, the Target address byte and the payload byte. There are 7 registers that can be addressed.
The address is 7 bits long. The TPS2363 is address selection uses A0 to A2, where no bit set is 1000000b,
1000001b (A0 only set), 1000010b (A1 only set), 1000011b (A0 + A1 set), 1000100b (A2 only set), 1000101b
(A0 + A2 set), 1000110b (A1 + A2 set) and 1000111b (A0, A1 + A2 set). The 8th bit is for read/write.
The SMBus can be used with direct mode operation, the registers will react different if AUXENA/B or ONA/B is
used than when they are turned on through the SMBus.
SMBus serial clock input terminal (SCL)
The SCL terminal allows the host controller to send a clock signal that synchronizes the data coming into or out
or the SDA terminal of the TPS2363. The frequency of this clock can be anywhere from 10 kHz and 400 kHz.
Timing diagrams show the relationship of the SCL to the SDA.
SMBus serial data input/output terminal (SDA)
The SDA terminal allows the host controller to program and read status from the TPS2363. Data sent into our out
of the SDA terminal is synchronous with the rising edge of SCL. Timing diagrams show the relationship between
SDA and SCL.
Copyright 2006–2010, Texas Instruments Incorporated
27
Product Folder Link(s): TPS2363
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