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參數(shù)資料
| 型號： | TPS2350DRG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 電源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO14 |
| 封裝： | GREEN, PLASTIC, MS-012AB, SOIC-14 |
| 文件頁數(shù)： | 22/26頁 |
| 文件大?。?/td> | 596K |
| 代理商： | TPS2350DRG4 |
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SLUS574C
– JULY 2003 – REVISED MARCH 2011
PIN FUNCTIONS
PIN
I/O
DESCRIPTION
NAME
NO.
FLT
2
O
Open-drain, active-low indication that the part is in fault.
FLTTIM
5
I/O
Connection for user programming of the fault timeout period.
Gate drive for external N-channel FET that ramps load current and disconnects in the event
GAT
11
O
of a fault.
GATA
9
O
Gate drive for external N-channel FET that selects
–VINA.
GATB
8
O
Gate drive for external N-channel FET that selects
–VINB.
OV
4
I
Over voltage sense input.
PG
12
O
Open-drain, active-high indication that the power FET is fully enhanced.
RAMP
6
I/O
Programming input for setting the inrush current slew rate.
RTN
1
I
Supply return (ground).
SENSE
10
I
Positive current sense input.
SOURCE
7
I/O
Negative current sense input.
UV
3
I
Under voltage sense input.
–VINA
14
I
Negative supply input A.
–VINB
13
I
Negative supply input B.
PIN DESCRIPTIONS
FLT: Open-drain, active-low indication that TPS2350 has shut down due to a faulted load. This happens if the
load current stays limited by the linear current amplifier for more than the fault time (time to charge the FLTTIM
capacitor). FLT is cleared when both supplies drop below the UV-comparator threshold or one supply exceeds
the OV-comparator threshold. The FLT output is pulled to the lower of
–VINA and –VINB. The FLT output is able
to sink 10 mA when in fault, withstand 80 V without leakage when not faulted, and withstand transients as high
as 100 V when limited by a series resistor of at least 10 k
Ω.
FLTTIM: Connection for user programming of the fault timeout period. An external capacitor connected from
FLTTIM to SOURCE establishes the timeout period to declare a fault condition. This timeout protects against
indefinite current sourcing into a faulted load, and also provides a filter against nuisance trips from momentary
current spikes or surges. TPS2350 define a fault condition as voltage at the SENSE pin at or greater than the
42-mV fault threshold. When a fault condition exists, the timer is active. The devices manage fault timing by
charging the external capacitor to the 4-V fault threshold, then subsequently discharging it at approximately 1%
the charge rate to establish the duty cycle for retrying the load. Whenever the fault latch is set (timer expired),
GAT and FLT are pulled low.
GAT: Gate drive for an external N-channel protection power MOSFET. When either input supply is above the UV
threshold and both are below the OV threshold, gate drive is enabled and the device begins charging the
external capacitor connected to RAMP. RAMP develops the reference voltage at the non-inverting input of the
internal LCA. The inverting input is connected to the current sense node, SENSE. The LCA acts to slew the pass
FET gate to force the SENSE voltage to track the reference. The reference is internally clamped to
42 mV, so the maximum current that can be sourced to the load is determined by the sense resistor value as
IMAX ≤ 42 mV/RSENSE. Once the load voltage has ramped up to the input dc potential and current demand drops
off, the LCA drives GAT 14 V above SOURCE to fully enhance the pass FET, completing the low-impedance
supply return path for the load.
GATA: Gate drive for an external N-channel power MOSFET to select
–VINA. When –VINA is more negative
than
–VINB, GATA is pulled 14 V above –VINA, turning on the –VINA power FET. When –VINB is more negative
than
–VINA, GATA is pulled down to –VINB, turning off the –VINA power FET.
Copyright
2003–2011, Texas Instruments Incorporated
5
Product Folder Link(s): TPS2350
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