參數(shù)資料
型號(hào)： TPS2350DRG4
廠(chǎng)商： TEXAS INSTRUMENTS INC
元件分類(lèi)： 電源管理
英文描述： 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO14
封裝： GREEN, PLASTIC, MS-012AB, SOIC-14
文件頁(yè)數(shù)： 20/26頁(yè)
文件大?。?/td> 596K
代理商： TPS2350DRG4
SLUS574C
– JULY 2003 – REVISED MARCH 2011
THERMAL INFORMATION
TPS2350
THERMAL METRIC(1)
UNITS
D (14 PINS)
PW (14 PINS)
θJA
Junction-to-ambient thermal resistance
95.9
120.8
θJB
Junction-to-board thermal resistance
51.5
62.8
θJCtop
Junction-to-case (top) thermal resistance
50.7
n/a
°C/W
ψJT
Junction-to-top characterization parameter
8.3
1
ψJB
Junction-to-board characterization parameter
51.1
56.5
(1)
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
ELECTRICAL CHARACTERISTICS
–VINA = –48 V, –VINB = 0 V, UV = 2.5 V, OV = 0.5 V, SENSE = 0 V, RAMP = 0 V, SOURCE = more negative of –VINA
and
–VINB, all outputs unloaded, TA = –40°C to 85°C (unless otherwise noted)
(1) (2)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Input Supply
ICC1A
Supply current
–VINA = –48 V, –VINB = 0 V
1000
1500
ICC2A
Supply current
–VINA = –80 V, –VINB = 0 V
2000
A
ICC1B
Supply current
–VINB = –48 V, –VINA = 0 V
1000
1500
ICC2B
Supply current
–VINB = –80 V, –VINA = 0 V
2000
VUVLO_I
Internal UVLO threshold voltage
To GAT pull up
–11.8
–10
–8.0
V
VHYST
Internal UVLO hysteresis voltage
50
240
500
mV
Overvoltage and Undervoltage Inputs (OV and UV)
To GAT pull up, 25
°C
1.391
1.400
1.409
UV threshold voltage, UV rising,
VTHUV
To GAT pull up, 0 to 70
°C
1.387
1.400
1.413
V
to
–VINA
To GAT pull up,
–40 to 85°C
1.384
1.400
1.419
IHYSUV
UV hysteresis
UV =
–45.5 V
–11
–10
–9
A
IILUV
UV low-level input current
UV =
–47 V
–1
1
OV threshold voltage, OV rising,
VTHOV
To GAT pull up
1.376
1.400
1.426
V
to
–VINA
IHYSOV
OV hysteresis
OV =
45.5 V
–11.1
–10
–8.6
A
IILOV
OV low-level input current
OV =
–47 V
–1
1
A
Linear Current Amplifier (LCA)
VOH
High level output, GAT
–SOURCE
SENSE = SOURCE
11
14
17
V
SENSE
– SOURCE = 80 mV,
ISINK_f
GAT sink current in fault
30
75
GAT =
–43 V, FLTTIME = 5 V
mA
SENSE
– SOURCE = 80 mV,
ISINK_l
GAT sink current in linear mode
5
10
GAT =
–43 V, FLTTIME = 2 V
IIN
SENSE input current
0.0 V
< SENSE – SOURCE < 0.2 V
–1
1
A
Reference clamp voltage, SENSE
–
VREF_K
RAMP
– SOURCE = 6 V
34
42
50
SOURCE
mV
Input offset voltage, SENSE
–
VIO
RAMP
– SOURCE = 0 V
–7
9
SOURCE
Ramp Generator
ISRC1
RAMP source current, slow turn-on rate RAMP
SOURCE = 0.25 V
–800
–550
–300
nA
ISRC2
RAMP source current, normal rate
RAMP
– SOURCE = 1 V and 3 V
–11.3
–10
–8.5
μA
VOL
Low-level output voltage
UV = SOURCE
5
mV
AV
Voltage gain, relative to SENSE
0 V
< RAMP – SOURCE < 5 V
9.5
10
10.7
mV/V
(1)
All voltages are with respect to RTN unless otherwise stated.
(2)
Currents are positive into and negative out of the specified terminal.
Copyright
2003–2011, Texas Instruments Incorporated
3
Product Folder Link(s): TPS2350
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