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參數(shù)資料
| 型號： | TPS2321IDG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 電源管理 |
| 英文描述： | 2-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO16 |
| 封裝： | GREEN, PLASTIC, MS-012AC, SOIC-16 |
| 文件頁數(shù)： | 9/28頁 |
| 文件大?。?/td> | 747K |
| 代理商： | TPS2321IDG4 |
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TIMER
OUTPUT-VOLTAGE SLEW-RATE CONTROL
dVs
dt
+
15 mA
C
gd
(1)
VREG CAPACITOR
GATE-DRIVE CIRCUITRY
SLVS276E – MARCH 2000 – REVISED NOVEMBER 2006
APPLICATION INFORMATION (continued)
Table 2. Some Available N-Channel MOSFETs (continued)
CURRENT RANGE
PART NUMBER
DESCRIPTION
MANUFACTURER
(A)
IRF7401
N-channel, rDS(on) = 0.022 , 7 A, SO-8
International Rectifier
MMSF5N02HDR2
N-channel, rDS(on) = 0.025 , 5 A, SO-8
ON Semiconductor
2 to 5
IRF7313
Dual N-channel, rDS(on) = 0.029 , 5.2 A, SO-8
International Rectifier
SI4410
N-channel, rDS(on) = 0.020 , 8 A, SO-8
Vishay Dale
IRLR3103
N-channel, rDS(on) = 0.019 , 29 A, d-Pak
International Rectifier
5 to 10
IRLR2703
N-channel, rDS(on) = 0.045 , 14 A, d-Pak
International Rectifier
For most applications, a minimum capacitance of 50 pF is recommended to prevent false triggering. A capacitor
should be connected between TIMER and ground. The presence of an overcurrent condition on either channel
of the TPS2320/TPS2321 causes a 50-
A current source to begin charging this capacitor. If the over-current
condition persists until the capacitor has been charged to approximately 0.5 V, the TPS2320/TPS2321 latches
off the offending channels and pulls the FAULT pin low. The timer capacitor can be made as large as desired to
provide additional time delay before registering a fault condition. PWRGDx will not correctly report power
conditions when the device is disabled. The time delay is approximately:
dt(sec) = CTIMER(F) × 10,000().
When enabled, the TPS2320/TPS2321 controllers supply the gates of each external MOSFET transistor with a
current of approximately 15
A. The slew rate of the MOSFET source voltage is thus limited by the gate-to-drain
capacitance Cgd of the external MOSFET capacitor to a value approximating:
If a slower slew rate is desired, an additional capacitance can be connected between the gate of the external
MOSFET and ground.
The internal voltage regulator connected to VREG requires an external capacitor to ensure stability. A 0.1-F or
0.22-F ceramic capacitor is recommended.
The TPS2320/TPS2321 includes four separate features associated with each gate-drive terminal:
A charging current of approximately 15 A is applied to enable the external MOSFET transistor. This current
is generated by an internal charge pump that can develop a gate-to-source potential (referenced to DISCH1
or DISCH2) of 9 V–12 V. DISCH1 and DISCH2 must be connected to the respective external MOSFET
source terminals to ensure proper operation of this circuitry.
A discharge current of approximately 75 A is applied to disable the external MOSFET transistor. Once the
transistor gate voltage has dropped below approximately 1.5 V, this current is disabled and the UVLO
discharge driver is enabled instead. This feature allows the part to enter a low-current shutdown mode while
ensuring that the gates of the external MOSFET transistors remain at a low voltage.
During a UVLO condition, the gates of both MOSFET transistors are pulled down by internal PMOS
transistors. These transistors continue to operate even if IN1 and IN2 are both at 0 V. This circuitry also
helps hold the external MOSFET transistors off when power is suddenly applied to the system.
During an overcurrent fault condition, the external MOSFET transistor that exhibited an overcurrent condition
will be rapidly turned off by an internal pulldown circuit capable of pulling in excess of 400 mA (at 4 V) from
the pin. Once the gate has been pulled below approximately 1.5 V, this driver is disengaged and the UVLO
driver is enabled instead. If one channel experiences an overcurrent condition and the other does not, then
17
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