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SETTING THE CURRENT-LIMIT CIRCUIT-BREAKER THRESHOLD
I
LMT1 +
R
ISET1
50
10–6
R
ISENSE1
(2)
UNDERVOLTAGE LOCKOUT (UVLO)
SINGLE-CHANNEL OPERATION
POWER-UP CONTROL
3-CHANNEL HOT-SWAP APPLICATION
SLVS276E – MARCH 2000 – REVISED NOVEMBER 2006
only the channel that is conducting excessive current will be turned off rapidly. The other channel will
continue to operate normally.
Using channel 1 as an example, the current sensing resistor RISENSE1 and the current-limit-setting resistor RISET1
determine the current limit of the channel, and can be calculated by the following equation:
Typically RISENSE1 is very small (0.001 to 0.1 ). If the trace and solder-junction resistances between the
junction of RISENSE1 and ISENSE1 and the junction of RISENSE1 and RISET1 are greater than 10% of the RISENSE1
value, then these resistance values should be added to the RISENSE1 value used in the calculation above.
The above information and calculation also apply to channel 2.
Table 3 shows some of the current sense
resistors available in the market.
Table 3. Some Current Sense Resistors
CURRENT RANGE (A)
PART NUMBER
DESCRIPTION
MANUFACTURER
0 to 1
WSL-1206, 0.05 1%
0.05
, 0.25 W, 1% resistor
1 to 2
WSL-1206, 0.025 1%
0.025
, 0.25 W, 1% resistor
2 to 4
WSL-1206, 0.015 1%
0.015
, 0.25 W, 1% resistor
Vishay Dale
4 to 6
WSL-2010, 0.010 1%
0.010
, 0.5 W, 1% resistor
6 to 8
WSL-2010, 0.007 1%
0.007
, 0.5 W, 1% resistor
8 to 10
WSR-2, 0.005 1%
0.005
, 0.5 W, 1% resistor
The TPS2320/TPS2321 includes an undervoltage lockout (UVLO) feature that monitors the voltage present on
the VREG pin. This feature will disable both external MOSFETs if the voltage on VREG drops below 2.78 V
(nominal) and will re-enable normal operation when it rises above 2.85 V (nominal). Since VREG is fed from IN1
through a low-dropout voltage regulator, the voltage on VREG will track the voltage on IN1 within 50 mV. While
the undervoltage lockout is engaged, both GATE1 and GATE2 are held low by internal PMOS pulldown
transistors, ensuring that the external MOSFET transistors remain off at all times, even if all power supplies have
fallen to 0 V.
Some applications may require only a single external MOS transistor. Such applications should use GATE1 and
the associated circuitry (IN1, ISENSE1, ISET1, DISCH1). The IN2 pin should be grounded to disable the
circuitry associated with the GATE2 pin.
The TPS2320/TPS2321 includes a 500
s (nominal) startup delay that ensures that internal circuitry has
sufficient time to start before the device begins turning on the external MOSFETs. This delay is triggered only
upon the rapid application of power to the circuit. If the power supply ramps up slowly, the undervoltage lockout
circuitry will provide adequate protection against undervoltage operation.
Some applications require hot-swap control of up to three voltage rails, but may not explicitly require the sensing
of the status of the output power on all three of the voltage rails. One such application is device bay, where dv/dt
control of 3.3 V, 5 V, and 12 V is required. By using Channel 2 to drive both the 3.3-V and 5-V power rails and
Channel 1 to drive the 12-V power rail, as is shown below, TPS2320/01 can deliver three different voltages to
three loads while monitoring the status of two of the loads.
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