參數(shù)資料
型號: TPM754A
廠商: NXP Semiconductors N.V.
英文描述: Microcontroller with TrackPoint microcode from IBM(IBM的帶有磁道點微碼的微控制器)
中文描述: 微控制器,帶有軌跡球來自IBM的微碼(IBM公司的帶有磁道點微碼的微控制器)
文件頁數(shù): 3/12頁
文件大?。?/td> 81K
代理商: TPM754A
Philips Semiconductors
Preliminary specification
TPM754A
Microcontroller with TrackPoint
microcode from IBM
1999 Nov 11
3
PIN DESCRIPTION
MNEMONIC
DIP
PIN NO.
TYPE
NAME AND FUNCTION
V
SS
8
I
Circuit Ground Potential.
V
CC
P1.0–P1.2
22
I
Supply voltage during normal, idle, and power-down operation.
21, 23, 24
I/O
Port 1:
Port 1 is a 3-bit bidirectional I/O port with internal pull-ups on P1.0 and P1.1. Port 1 pins that
have 1s written to them can be used as inputs. As inputs, port 1 pins that are externally pulled low will
source current because of the internal pull-ups (P1.0, P1.1). (See DC Electrical Characteristics: I
IL
).
Port 1 also serves the special function features listed below (Note: P1.0 does
not
have the strong
pullup that is on for 2 oscillator periods.):
INT0 (P1.0):
External interrupt 0.
CEX (P1.1):
PCA clock output.
24
23
I
O
P3.0–P3.7
1–4,
25–28
I/O
Port 3:
Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s written to
them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 3 pins that are
externally being pulled low will source current because of the pull-ups. (See DC Electrical
Characteristics: I
IL
). (Note: P3.5 does
not
have the strong pullup that is on for 2 oscillator periods.)
Port 3 also serves the special function as listed below:
ECI (P3.6):
External PCA clock input.
RxD/T0 (P3.4):
Serial port receiver data input.
Timer 0 external clock input.
INT1:
External interrupt 1.
TxD/T1 (P3.5):
Serial port transmitter data.
Timer 1 external clock input.
3
1
I
I
4
2
I
I
RST
5
I
Reset:
A high on this pin for two machine cycles while the oscillator is running resets the device.
(NOTE: The TPM754 does not have an internal reset resistor.)
X1
7
I
Crystal 1:
Input to the inverting oscillator amplifier and input to the internal clock generator circuits.
X2
AV
CC 1
AV
SS 1
ZIN
6
O
Crystal 2:
Output from the inverting oscillator amplifier.
14
I
Analog supply voltage and reference input.
13
I
Analog supply and reference ground.
9
I
ZIN:
Input to analog multiplexer.
YIN
10
I
YIN:
Input to analog multiplexer.
XIN
11
I
XIN:
Input to analog multiplexer.
XYZRAMP
12
O
XYZRAMP:
Provides a low impedance pulldown to V
SS
under S/W control.
DECOUPLE:
Output from regulated supply for connection of decoupling capacitors.
DECOUPLE
15
O
VREG
16
O
VREG:
Provides regulated analog supply output.
XYDACBIAS
17
O
XYDACBIAS:
Provides source voltage for bias of external circuitry.
XYSOURCE
18
O
XYSOURCE:
Provides source voltage from regulated analog supply.
ZDAC
19
O
ZDAC:
Switchable output from the internal DAC.
XYDAC
NOTE:
1. AV
SS
(reference ground) must be connected to 0 V (ground). AV
CC
(reference input) cannot differ from V
CC
by more than
±
0.2 V, and must
be in the range 4.5 V to 5.5 V.
20
O
XYDAC:
Non-switchable output from the internal DAC.
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