參數(shù)資料
型號(hào)： TPA6017A2PWPR
元件分類： 音頻放大器
英文描述： AUDIO AMPLIFIER|DUAL|CMOS|TSSOP|20PIN|PLASTIC
中文描述： 音頻放大器|雙|的CMOS | TSSOP封裝| 20針|塑料
文件頁(yè)數(shù)： 19/33頁(yè)
文件大?。?/td> 469K
代理商： TPA6017A2PWPR
TPA6011A4
SLOS392
–
FEBRUARY 2002
19
www.ti.com
APPLICATION INFORMATION
shutdown modes
The TPA6011A4 employs a shutdown mode of operation designed to reduce supply current (I
DD
) to the absolute
minimum level during periods of nonuse for battery-power conservation. The SHUTDOWN input terminal
should be held high during normal operation when the amplifier is in use. Pulling SHUTDOWN low causes the
outputs to mute and the amplifier to enter a low-current state, I
DD
= 20
μ
A. SHUTDOWN should never be left
unconnected because amplifier operation would be unpredictable.
Table 3. HP/LINE, SE/BTL, and Shutdown Functions
INPUTS
SE/BTL
AMPLIFIER STATE
HP/LINE
SHUTDOWN
INPUT
OUTPUT
X
X
Low
X
Mute
Low
Low
High
Line
BTL
Low
High
High
Line
SE
High
Low
High
HP
BTL
High
High
High
HP
SE
Inputs should never be left unconnected.
X = don
’
t care
NOTE: The
Low
and
High
trip levels can be found in the
recommended operating conditions
table.
FADE operation
For design flexibility, a fade mode is provided to slowly ramp up the amplifier gain when coming out of shutdown
mode and conversely ramp the gain down when going into shutdown. This mode provides a smooth transition
between the active and shutdown states and virtually eliminates any pops or clicks on the outputs.
When the FADE input is a logic low, the device is placed into fade-on mode. A logic high on this pin places the
amplifier in the fade-off mode. The voltage trip levels for a logic low (V
IL
) or logic high (V
IH
) can be found in the
recommended operating conditions
table on page 4.
When a logic low is applied to the FADE pin and a logic low is then applied on the SHUTDOWN pin, the channel
gain steps down from gain step to gain step at a rate of two clock cycles per step. With a nominal internal clock
frequency of 58 Hz, this equates to 34 ms (1/24 Hz) per step. The gain steps down until the lowest gain step
is reached. The time it takes to reach this step depends on the gain setting prior to placing the device in
shutdown. For example, if the amplifier is in the highest gain mode of 20 dB, the time it takes to ramp down the
channel gain is 1.05 seconds. This number is calculated by taking the number of steps to reach the lowest gain
from the highest gain, or 31 steps, and multiplying by the time per step, or 34 ms.
After the channel gain is stepped down to the lowest gain, the amplifier begins discharging the bypass capacitor
from the nominal voltage of V
DD
/2 to ground. This time is dependent on the value of the bypass capacitor. For
a 0.47-
μ
F capacitor that is used in the application diagram in Figure 27, the time is approximately 500 ms. This
time scales linearly with the value of bypass capacitor. For example, if a 1-
μ
F capacitor is used for bypass, the
time period to discharge the capacitor to ground is twice that of the 0.47-
μ
F capacitor, or 1 second. Figure 30
below is a waveform captured at the output during the shutdown sequence when the part is in fade-on mode.
The gain is set to the highest level and the output is at V
DD
when the amplifier is shut down.
When a logic high is placed on the SHUTDOWN pin and the FADE pin is still held low, the device begins the
start-up process. The bypass capacitor will begin charging. Once the bypass voltage reaches the final value
of V
DD
/2, the gain increases in 2-dB steps from the lowest gain level to the gain level set by the dc voltage applied
to the VOLUME, SEDIFF, and SEMAX pins.
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