SLOS524D – JUNE 2008 – REVISED AUGUST 2009..........................." />
參數(shù)資料
型號: TPA2016D2RTJR
廠商: Texas Instruments
文件頁數(shù): 21/39頁
文件大?。?/td> 0K
描述: IC AMP AUDIO PWR 2.8W D 20QFN
標(biāo)準(zhǔn)包裝: 1
類型: D 類
輸出類型: 2 通道(立體聲)
在某負(fù)載時最大輸出功率 x 通道數(shù)量: 2.8W x 2 @ 4 歐姆
電源電壓: 2.5 V ~ 5.5 V
特點: 差分輸入,I²C,短路和熱保護,關(guān)機,音量控制
安裝類型: 表面貼裝
供應(yīng)商設(shè)備封裝: 20-QFN 裸露焊盤(4x4)
封裝/外殼: 20-WFQFN 裸露焊盤
包裝: 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁面: 876 (CN2011-ZH PDF)
其它名稱: 296-25430-6
COMPONENT LOCATION
TRACE WIDTH
SLOS524D – JUNE 2008 – REVISED AUGUST 2009........................................................................................................................................................ www.ti.com
Figure 41. Land Pattern Dimensions
Table 5. Land Pattern Dimensions(1) (2) (3) (4)
SOLDER PAD
SOLDER MASK(5)
COPPER
STENCIL
COPPER PAD
STENCIL(6) (7) OPENING
DEFINITIONS
OPENING
THICKNESS
275
m
375
m
Non solder mask
275
m × 275 m Sq. (rounded
1 oz max (32
m)
125
m thick
defined (NSMD)
corners)
(+0.0, –25
m)
(+0.0, –25
m)
(1)
Circuit traces from NSMD defined PWB lands should be 75
m to 100 m wide in the exposed area inside the solder mask opening.
Wider trace widths reduce device stand off and impact reliability.
(2)
Best reliability results are achieved when the PWB laminate glass transition temperature is above the operating the range of the
intended application.
(3)
Recommend solder paste is Type 3 or Type 4.
(4)
For a PWB using a Ni/Au surface finish, the gold thickness should be less 0.5 mm to avoid a reduction in thermal fatigue performance.
(5)
Solder mask thickness should be less than 20
m on top of the copper circuit pattern
(6)
Best solder stencil performance is achieved using laser cut stencils with electro polishing. Use of chemically etched stencils results in
inferior solder paste volume control.
(7)
Trace routing away from WCSP device should be balanced in X and Y directions to avoid unintentional component movement due to
solder wetting forces.
Place all the external components very close to the TPA2016D2. Placing the decoupling capacitor, CS, close to
the TPA2016D2 is important for the efficiency of the Class-D amplifier. Any resistance or inductance in the trace
between the device and the capacitor can cause a loss in efficiency.
Recommended trace width at the solder balls is 75
m to 100 m to prevent solder wicking onto wider PCB
traces. For high current pins (PVDD (L, R), PGND, and audio output pins) of the TPA2016D2, use 100-
m trace
widths at the solder balls and at least 500-
m PCB traces to ensure proper performance and output power for
the device. For the remaining signals of the TPA2016D2, use 75-
m to 100-m trace widths at the solder balls.
The audio input pins (INR± and INL±) must run side-by-side to maximize common-mode noise cancellation
28
Copyright 2008–2009, Texas Instruments Incorporated
Product Folder Link(s): TPA2016D2
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