參數(shù)資料
型號(hào): TPA2016D2RTJR
廠商: Texas Instruments
文件頁數(shù): 13/39頁
文件大小: 0K
描述: IC AMP AUDIO PWR 2.8W D 20QFN
標(biāo)準(zhǔn)包裝: 1
類型: D 類
輸出類型: 2 通道(立體聲)
在某負(fù)載時(shí)最大輸出功率 x 通道數(shù)量: 2.8W x 2 @ 4 歐姆
電源電壓: 2.5 V ~ 5.5 V
特點(diǎn): 差分輸入,I²C,短路和熱保護(hù),關(guān)機(jī),音量控制
安裝類型: 表面貼裝
供應(yīng)商設(shè)備封裝: 20-QFN 裸露焊盤(4x4)
封裝/外殼: 20-WFQFN 裸露焊盤
包裝: 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁面: 876 (CN2011-ZH PDF)
其它名稱: 296-25430-6
Register(N)
8-BitDatafor
Register(N+1)
SINGLE-AND MULTIPLE-BYTE TRANSFERS
SINGLE-BYTE WRITE
A6
A5
A4
A3
A2
A1
A0
R/W ACK A7
A6
A5
A4
A3
A2
A1
A0 ACK
D7
D6
D5
D4
D3
D2
D1
D0
ACK
Start
Condition
Stop
Condition
Acknowledge
I2CDeviceAddressand
Read/WriteBit
Register
DataByte
SLOS524D – JUNE 2008 – REVISED AUGUST 2009........................................................................................................................................................ www.ti.com
address and the read/write (R/W) bit to open communication with another device, and then waits for an
acknowledge condition. The TPA2016D2 holds SDA low during the acknowledge clock period to indicate
acknowledgment. When this acknowledgment occurs, the master transmits the next byte of the sequence. Each
device is addressed by a unique 7-bit slave address plus R/W bit (1 byte). All compatible devices share the same
signals via a bidirectional bus using a wired-AND connection.
An external pull-up resistor must be used for the SDA and SCL signals to set the logic high level for the bus.
When the bus level is 5 V, use pull-up resistors between 1 k
and 2 k.
Figure 36. Typical I2C Sequence
There is no limit on the number of bytes that can be transmitted between start and stop conditions. When the last
word transfers, the master generates a stop condition to release the bus. A generic data transfer sequence is
shown in Figure 36.
The serial control interface supports both single-byte and multi-byte read/write operations for all registers.
During multiple-byte read operations, the TPA2016D2 responds with data, one byte at a time, starting at the
register assigned, as long as the master device continues to respond with acknowledgments.
The TPA2016D2 supports sequential I2C addressing. For write transactions, if a register is issued followed by
data for that register and all the remaining registers that follow, a sequential I2C write transaction has occurred.
For I2C sequential write transactions, the register issued then serves as the starting point, and the amount of
data subsequently transmitted, before a stop or start is transmitted, determines the number of registers written.
As Figure 37 shows, a single-byte data write transfer begins with the master device transmitting a start condition
followed by the I2C device address and the read/write bit. The read/write bit determines the direction of the data
transfer. For a write data transfer, the read/write bit must be set to '0'. After receiving the correct I2C device
address and the read/write bit, the TPA2016D2 responds with an acknowledge bit. Next, the master transmits the
register byte corresponding to the TPA2016D2 internal memory address being accessed. After receiving the
register byte, the TPA2016D2 again responds with an acknowledge bit. Next, the master device transmits the
data byte to be written to the memory address being accessed. After receiving the register byte, the TPA2016D2
again responds with an acknowledge bit. Finally, the master device transmits a stop condition to complete the
single-byte data write transfer.
Figure 37. Single-Byte Write Transfer
20
Copyright 2008–2009, Texas Instruments Incorporated
Product Folder Link(s): TPA2016D2
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