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參數(shù)資料
| 型號(hào)： | TPA0211DGNR |
| 元件分類： | 音頻放大器 |
| 英文描述： | AUDIO AMPLIFIER|SINGLE|CMOS|TSSOP|8PIN|PLASTIC |
| 中文描述： | 音頻放大器|單|的CMOS | TSSOP封裝| 8引腳|塑料 |
| 文件頁(yè)數(shù)： | 33/42頁(yè) |
| 文件大?。?/td> | 806K |
| 代理商： | TPA0211DGNR |
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TPA0202
2-W STEREO AUDIO POWER AMPLIFIER
SLOS205B – FEBRUARY 1998 – REVISED DECEMBER 2000
33
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
SE/BTL
Rm2
100 k
Rm1
100 k
VDD
Left
Channel
From GPIO
Right
Channel
0.1
μ
F
Figure 66. Implementation with a Diode
The OR gate and diode isolate the GPIO terminal from the headphone switch. In these implementations, the
headphone switch has priority.
When the amplifier is in mute mode, the output stage continues to be biased. This causes the transition out of
mute mode to be very fast with only a short delay (from 100 ms to 500 ms). During power up or the transition
out of shutdown mode, a longer delay ( from 1 s to 2 s) is required. The exact delay time required is dependent
on the values of the external components used with the amplifier (see Figure 67).
System Control:
MUTE or SHUTDOWN
Delay
Output of Delay Circuit
(Input to SE/BTL)
Figure 67. Transition Delay Timing
single-ended operation
In SE mode (see Figure 59 and Figure 60), the load is driven from the primary amplifier output for each channel
(OUT+, terminals 22 and 3).
In SE mode the gain is set by the R
F
and R
I
resistors and is shown in equation 11. Since the inverting amplifier
is not used to mirror the voltage swing on the load, the factor of 2, from equation 5, is not included.
(11)
SE Gain
R
F
R
I
The output coupling capacitor required in single-supply SE mode also places additional constraints on the
selection of other components in the amplifier circuit. The rules described earlier still hold with the addition of
the following relationship (see equation 12):
(12)
1
C
B
25 k
1
C
I
R
I
1
R
L
C
C
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