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參數(shù)資料
| 型號： | TOSCA |
| 英文描述： | TOSCA (STLC60134 STLC60135) ADSL MODEM CHIP SET |
| 中文描述： | 托斯卡（STLC60134 STLC60135）ADSL調(diào)制解調(diào)器芯片組 |
| 文件頁數(shù)： | 2/7頁 |
| 文件大?。?/td> | 62K |
| 代理商： | TOSCA |
Interleaving is optional and can be used simulta-
neously on a slow channel (e.g., for data or con-
trol info) while a fast channel (e.g., video) oper-
ates
without
interleaving.
adaptation capabilities during show time.
In transmit direction the chip set allows to select
an attenuationof the signal in case of short loops
or largeecho (politeness). In receivedirection the
chip set can optionally control an external multi-
plexer to select an externalattenuationof the sig-
nal in case of short loops.
ICs
include
rate
TOSCA chip set
TOSCA is a two-chip ADSL modem transceiver.
ST also provides the necessary software for
transceiver’sexternalcontroller.
TOSCA can easily be hooked up with ATM sys-
tems through the built-in UTOPIA level 2 inter-
face. That allows ATM traffic to be carried, at up
to 8Mbit/s downstream and 1Mbit/s upstream,
over a veryplain and widespreadtwisted pair.
TOSCA can be used at both ends of the loop
(ATU-C and ATU-R ends).
The modem control software can be compiled as
C++ code,independentlyon the processor used.
The driver can be interfaced to any external real
time operatingsystem.
These pages blockdiagrams show the main func-
tionsbuilt-in in STLC60134and STLC60135.
TOSCA chip set supports three different rate ad-
aptation modes: fixed rate adaptationmode, fixed
with capability to boost within fixed range, dy-
namic rate adaptationduring show time.
Modem’s performances are set by the following
parameters: Rate adaptationmode, Downstream
and Upstream bit rate for both latency paths,
Noise margins (min, max and target typically at
10E-7 BER without RS, interleaving and trellis),
Maximum power spectraldensity for downstream,
Maximum power for both up and downstream,
Carrier mask (which tones are disabled), maxi-
mum interleaving delay.
Tones from number 8 to number 255 can be
used: from 8 to 31 for upsteam signals and from
32 to 255 for downstream signals. Numbers 16
and 64
are dedicated to pilot tones which are
employed for synchronisation purposes between
ATU-C and ATU-R ends. The software sets the
use of tonesfor optimisationof performances.
At ATU-R, time recovery is carried out by the
chip-set through the pilot tones. This activity is
undertaken in two steps in order to achieve no
more than 2ppm between ATU-C and ATU-R.
The transceiver controller software monitors line
and channel. As far as line is concerned noise
margin, attenuation, power, carrier load, relative
capacity occupation are
monitoring deals with cell-delineation,actual ATM
(fast and interleaved) up and downstream rates,
achievableATM DS and US rates (only at ATU-C
side).
checked. Channel’s
TOSCA ICs
TOSCA consists
(STLC60134) and a Discrete Multitone Modem
(STLC60135) integrated circuits which are pro-
duced by STMicroelectronics.
Here below we will briefly go through the main
topics of boththe ICs.
of an
Analog Front
End
DAC
MUX
4
12 bits/8.8MHz
DAC
MUX
4
12 bits/8.8MHz
ADC
MUX
4
12 bits/8.8MHz
TRANSMIT-SIDE
LPF
1.1MHz
LPF
138KHz
LPF
1.1MHz
LPF
138KHz
ATU-R
ATU-R
ATU-C
ATU-C
LPF
138KHz
LPF
1.1MHz
ATU-R
ATU-C
VCODAC
XTAL
DRIVER
G=15...0dB
STEP 1dB
G=15...0dB
STEP 1dB
35.328MHz
G=0...31dB
STEP 1dB
D98TL391
AGC
AGC
LNA
RECEIVE-SIDE
Figure 2. Analog FrontEnd block diagram.
TOSCA STLC60134/STLC60135
2/7
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