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參數(shù)資料
| 型號： | TNETA1611 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | STS-12c/STM-4 Receiver/Transimitter(STS-12C/STM-4接收/傳送器) |
| 中文描述： | STS-12c/STM-4接收器/ Transimitter（STS-12C/STM-4接收/傳送器） |
| 文件頁數(shù)： | 3/9頁 |
| 文件大小： | 189K |
| 代理商： | TNETA1611 |
TNETA1611
STS-12c/STM-4 RECEIVER/TRANSMITTER
SDNS035E – AUGUST 1995 – REVISED JUNE 1996
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
receive operation
Serial data is provided to the TNETA1611 on true and complement pseudo-ECL-compatible inputs (RSDT and
RSDC). A 622.08-MHz pseudo-ECL-compatible clock (RSCT and RSDC) must accompany the data such that
the data is valid on the rising edge of the true clock (RSCT) signal. The serial data is converted to byte-wide
data and directed out on RPD0–RPD7. This output data is accompanied by a clock (RPCK). RPD0–RPD7 and
RPCK are TTL-compatible outputs.
The TNETA1611 utilizes the out-of-frame (OOF) signal generated by subsequent processing elements for bit
alignment. When OOF goes high, the TNETA1611 begins searching the received data for a string of 12
consecutive A1 bytes (12 hex F6s). Once this sequence is found, the TNETA1611 aligns the byte-wide data
output with the A1-byte boundaries so that subsequent data (i.e., the A2 bytes) is properly aligned. The
subsequent processing element (i.e., a framer) must detect and monitor the byte-aligned data for complete
SONET/SDH framing patterns (12 A1s followed by 12 A2s) to ensure standards compliance for functions like
loss of frame, etc. The TNETA1611 does not realign the output when OOF is low.
An output-enable (OE) terminal is provided to enable/disable all TTL outputs. When OE is low, RPCK,
RPD0–RPD7, and TPCK are held in the high-impedance state. When OE is high, these terminals function as
previously described.
Receive functions are reset by taking RESET low. This action can result in the loss of any data being processed.
data/clock source control
There are three control inputs to the TNETA1611 that change the source of data (and/or clock) for a given output.
The effects of these inputs (OE, CLKLOOP, and FLB) are indicated in the following table.
STATE OF CONTROL INPUTS
SOURCE OF DATA/CLOCK FOR OUTPUTS
OE
CLKLOOP
FLB
TSDT/TSDC
N/A
TSCT/TSCC
TPCK
RPDO–RPD7
RPCK
0
0
0
TXHCKT/TXHCKC
High impedance
High impedance
High impedance
0
0
1
RSDT/RSDC
N/A
RSCT/RSCC
High impedance
High impedance
High impedance
0
1
0
RSCT/RSCC
High impedance
High impedance
High impedance
0
1
1
RSDT/RSDC
RSCT/RSCC
High impedance
High impedance
High impedance
1
0
0
TPD0–TPD7
TXHCKT/TXHCKC
TXHCKT/TXHCKC
RSDT/RSDC
RSCT/RSCC
1
0
1
RSDT/RSDC
RSCT/RSCC
RSCT/RSCC
RSDT/RSDC
RSCT/RSCC
1
1
0
TPD0–TPD7
RSCT/RSCC
RSCT/RSCC
RSDT/RSDC
RSCT/RSCC
1
1
1
RSDT/RSDC
RSCT/RSCC
RSCT/RSCC
RSDT/RSDC
RSCT/RSCC
This is not a normal operating condition. As no clock is output on TPCK, valid data cannot be properly input on TPD0–TPD7; thus, the data output
on TSDT/TSDC may be invalid.
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