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參數(shù)資料
| 型號(hào)： | TNETA1611 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | STS-12c/STM-4 Receiver/Transimitter(STS-12C/STM-4接收/傳送器) |
| 中文描述： | STS-12c/STM-4接收器/ Transimitter（STS-12C/STM-4接收/傳送器） |
| 文件頁數(shù)： | 2/9頁 |
| 文件大小： | 189K |
| 代理商： | TNETA1611 |
TNETA1611
STS-12c/STM-4 RECEIVER/TRANSMITTER
SDNS035E – AUGUST 1995 – REVISED JUNE 1996
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
functional block diagram
RSDT
RSDC
RSCT
RSCC
Data/
Clock
MUX
Parallel-to-Serial
Conversion
RPCK
RPD0–RPD7
OOF
Serial-to-Parallel
Conversion
and Bit
Alignment
RESET
OE
FLB
TXHCKT
TXHCKC
TSCT
TSCC
TSDT
TSDC
8
CLKLOOP
TPCK
TPD0–TPD7
8
RTNCK
detailed description
transmit operation
The transmit parallel interface consists of TTL-compatible byte-wide input data (TPD0–TPD7), a
TTL-compatible transmit output clock (TPCK), and a TTL-compatible return clock input (RTNCK). TPCK is an
output to associated processing elements (i.e., a framer) that controls the output of byte-wide transmit data from
such devices. The return clock and data are input to the TNETA1611 such that byte-wide transmit data
(TPD0–TPD7) is clocked into the TNETA1611 on low-to-high transitions of RTNCK. If a return clock is not
available, RTNCK can be tied to TPCK provided the timing requirements between TPCK and TPD0–TPD7 can
be met.
The byte-wide data is converted to a 622.08-Mbit/s serial-data stream that is sent out differentially on transmit
serial-data true (TSDT) and transmit serial-data complement (TSDC). In addition, a phase-aligned 622.08-MHz
clock is sent out differentially on transmit serial-clock true (TSCT) and transmit serial-clock complement
(TSCC). The serial output data is valid on the rising edge of TSCT. TSDT, TSDC, TSCT, and TSCC are
pseudo-ECL-compatible outputs.
The transmit clock source can come from either of two inputs. If transmit clock loop (CLKLOOP) is low, an
external 622.08-MHz clock source is used. This differential transmit high-speed clock input enters on pseudo-
ECL-compatible terminals TXHCKT and TXHCKC. If CLKLOOP is high, the receive serial clock (RSCT and
RSCC) input with the receive data stream is used for transmit operations.
A facility-loopback (FLB) option is also available. When FLB is high, data input into the receiver and the
corresponding clock are looped back and provided at the transmitter outputs. This allows a method for loopback
testing in a system.
Transmit functions are reset by taking RESET low. This action can result in the loss of any data being processed.
P
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