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TMS320TCI6482
Communications Infrastructure Digital Signal Processor
SPRS246F–APRIL 2005–REVISED MAY 2007
Table 3-9. Peripheral Status Register 0 (PERSTAT0) Field Descriptions (continued)
Bit
2:0
Field
TCPSTAT
Value
Description
TCP status
TCP is in the disabled state
TCP is in the enabled state
TCP is in the static powerdown state
TCP is in the disable in progress state
TCP is in the enable in progress state
Reserved
000
001
011
100
101
Others
31
16
Reserved
R-0
15
14
12
11
9
8
6
5
3
2
0
Rsvd
RSA1STAT
RSA0STAT
VLYNQSTAT
UTOPIASTAT
PCISTAT
R-0
LEGEND:
R = Read only; -
n
= value after reset
R-0
R-0
R-0
R-0
R-0
Figure 3-7. Peripheral Status Register 1 (PERSTAT1) - 0x02AC 0018
Table 3-10. Peripheral Status Register 1 (PERSTAT1) Field Descriptions
Bit
31:15
14:12
Field
Reserved
RSA1STAT
Value
Description
Reserved.
RSA1 status
RSA1 is in the disabled state
RSA1 is in the enabled state
RSA1 is in the static powerdown state
RSA1 is in the disable in progress state
RSA1 is in the enable in progress state
Reserved
RSA0 status
RSA0 is in the disabled state
RSA0 is in the enabled state
RSA0 is in the static powerdown state
RSA0 is in the disable in progress state
RSA0 is in the enable in progress state
Reserved
VLYNQ status
VLYNQ is in the disabled state
VLYNQ is in the enabled state
VLYNQ is in the static powerdown state
VLYNQ is in the disable in progress state
VLYNQ is in the enable in progress state
Reserved
000
001
011
100
101
Others
11:9
RSA0STAT
000
001
011
100
101
Others
8:6
VLYNQSTAT
000
001
011
100
101
Others
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