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參數(shù)資料
| 型號(hào)： | TMX320TCI6482ZTZA |
| 廠商： | Texas Instruments, Inc. |
| 元件分類(lèi)： | 數(shù)字信號(hào)處理 |
| 英文描述： | Communications Infrastructure Digital Signal Processor |
| 中文描述： | 通信基礎(chǔ)設(shè)施的數(shù)字信號(hào)處理器 |
| 文件頁(yè)數(shù)： | 135/255頁(yè) |
| 文件大?。?/td> | 1893K |
| 代理商： | TMX320TCI6482ZTZA |
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TMS320TCI6482
Communications Infrastructure Digital Signal Processor
SPRS246F–APRIL 2005–REVISED MAY 2007
SYSCLK4 is used as the internal clock for the EMIFA and VLYNQ. It is also used to clock other logic
within the DSP.
SYSCLK5 clocks the emulation and trace logic of the DSP.
The divider ratio bits of dividers D2 and D3 are fixed at ÷3 and ÷6, respectively. The divider ratio bits of
dividers D4 and 54 are programmable through the PLL controller divider registers PLLDIV4 and PLLDIV5,
respectively.
The PLL multiplier controller (PLLM) and the dividers (D4 and D5) must be programmed after reset.
There
is no hardware CLKMODE selection on the TCI6482 device.
Since the divider ratio bits for dividers D2 and D3 are fixed, the frequency of SYSCLK2 and SYSCLK3 is
tied to the frequency of SYSREFCLK. However, the frequency of SYSCLK4 and SYSCLK5 depends on
the configuration of dividers D4 and D5. For example, with PLLM in the PLL1 multiply control register set
to 10011b (x20 mode) and a 50 MHz CLKIN1 input, the PLL output PLLOUT is set to 1000 MHz and
SYSCLK2 and SYSCLK3 run at 333 MHz and 166 MHz, respectively. Divider D4 can be programmed
through the PLLDIV4 register to divide SYSREFCLK by 10 such that SYSCLK4, and hence the EMIF
internal clock, runs at 100 MHz.
All hosts (HPI, PCI, etc.) must hold off accesses to the DSP while the frequency of its internal clocks is
changing. A mechanism must be in place such that the DSP notifies the host when the PLL configuration
has completed.
Note that there is a minimum and maximum operating frequency for PLLREF, PLLOUT, SYSCLK4, and
SYSCLK5. The PLL1 Controller must not be configured to exceed any of these constraints (certain
combinations of external clock input, internal dividers, and PLL multiply ratios might not be supported). For
the PLL clocks input and output frequency ranges, see
Table 8-16
.
Table 8-16. PLL1 Clock Frequency Ranges
CLOCK SIGNAL
MIN
MAX
66.6
66.6
1000
166
333
UNIT
MHz
MHz
MHz
MHz
MHz
CLKIN1
PLLREF (PLLEN = 1)
(1)
PLLOUT
(1)
SYSCLK4
SYSCLK5
33.3
400
25
(1)
8.7.1.2
Only applies when the PLL1 Controller is set to PLL mode (PLLEN = 1 in the PLLCTL register).
PLL1 Controller Operating Modes
The PLL1 controller has two modes of operation: bypass mode and PLL mode. The mode of operation is
determined by the PLLEN bit of the PLL control register (PLLCTL). In PLL mode, SYSREFCLK is
generated from the device input clock CLKIN1 using the divider PREDIV and the PLL multiplier PLLM. In
bypass mode, CLKIN1 is fed directly to SYSREFCLK.
All hosts (HPI, PCI, etc.) must hold off accesses to the DSP while the frequency of its internal clocks is
changing. A mechanism must be in place such that the DSP notifies the host when the PLL configuration
has completed.
8.7.1.3
PLL1 Stabilization, Lock, and Reset Times
The PLL stabilization time is the amount of time that must be allotted for the internal PLL regulators to
become stable after device powerup. The PLL should not be operated until this stabilization time has
expired.
The PLL reset time is the amount of wait time needed when resetting the PLL (writing PLLRST = 1), in
order for the PLL to properly reset, before bringing the PLL out of reset (writing PLLRST = 0). For the
PLL1 reset time value, see
Table 8-17
.
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C64x+ Peripheral Information and Electrical Specifications
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