
SPRS457E
– MARCH 2009 – REVISED JUNE 2011
Table 6-22. Switching Characteristics Over Recommended Operating Conditions for Asynchronous
DEVICE
UNI
NO.
PARAMETER
T
MIN
TYP
MAX
Output setup time, EM_A[21:0] valid to
8
tsu(EMBAV-EMOEL)
(RS + 1)*E
ns
EM_OE low
Output hold time, EM_OE high to
9
th(EMOEH-EMAIV)
(RH + 1)*E
ns
EM_A[21:0] invalid
EM_OE active low width (EW = 0)
(RST)*E
ns
10
tw(EMOEL)
EM_OE active low width (EW = 1)
(RST+(EWC*16))*E
ns
td(EMWAITH-
Delay time from EM_WAIT deasserted to
11
4E
ns
EMOEH)
EM_OE high
READS (OneNAND Synchronous Burst Read)
MH
32
fc(EM_CLK)
Frequency, EM_CLK
66
z
33
tc(EM_CLK)
Cycle time, EM_CLK
15.15
ns
tsu(EM_ADVV-
Output setup time, EM_ADV valid before
34
2E - 2.5
ns
EM_CLKH)
EM_CLK high
th(EM_CLKH-
Output hold time, EM_CLK high to EM_ADV
35
2E + 3
ns
EM_ADVIV)
invalid
tsu(EM_AV-
Output setup time, EM_A[21:0]/EM_BA[1]
36
2E - 2.5
ns
EM_CLKH)
valid before EM_CLK high
th(EM_CLKH-
Output hold time, EM_CLK high to
37
2E + 3
ns
EM_AIV)
EM_A[21:0]/EM_BA[1] invalid
38
tw(EM_CLKH)
Pulse duration, EM_CLK high
5.05
ns
39
tw(EM_CLKL)
Pulse duration, EM_CLK low
5.05
ns
WRITES
(WS + WST +
EMIF write cycle time (EW = 0)
WH + TA + 4) * E
ns
- 3
+ 3
15
tc(EMWCYCLE)
(WS + WST +
EMIF write cycle time (EW = 1)
WH + TA + 4) * E
ns
- 3
+ 3
Output setup time, EM_CE[1:0] low to
(WS+1) * E - 3
ns
EM_WE low (SS = 0)
16
tsu(EMCEL-EMWEL)
Output setup time, EM_CE[1:0] low to
(WS+1) * E - 3
ns
EM_WE low (SS = 1)
Output hold time, EM_WE high to
(WH+1) * E - 3
ns
EM_CE[1:0] high (SS = 0)
17
th(EMWEH-EMCEH)
Output hold time, EM_WE high to
(WH+1) * E - 3
ns
EM_CE[1:0] high (SS = 1)
Output setup time, EM_BA[1:0] valid to
20
tsu(EMBAV-EMWEL)
(WS+1) * E - 3
ns
EM_WE low
Output hold time, EM_WE high to
21
th(EMWEH-EMBAIV)
(WH+1) * E - 3
ns
EM_BA[1:0] invalid
Output setup time, EM_A[21:0] valid to
22
tsu(EMAV-EMWEL)
(WS+1) * E - 3
ns
EM_WE low
Output hold time, EM_WE high to
23
th(EMWEH-EMAIV)
(WH+1) * E - 3
ns
EM_A[21:0] invalid
EM_WE active low width (EW = 0)
(WST+1) * E - 3
ns
24
tw(EMWEL)
EM_WE active low width (EW = 1)
(WST+1) * E - 3
ns
td(EMWAITH-
Delay time from EM_WAIT deasserted to
25
4E + 3
ns
EMWEH)
EM_WE high
Output setup time, EM_D[15:0] valid to
26
tsu(EMDV-EMWEL)
(WS+1) * E - 3
ns
EM_WE low
Output hold time, EM_WE high to
27
th(EMWEH-EMDIV)
(WH+1) * E - 3
ns
EM_D[15:0] invalid
102
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