參數(shù)資料
型號(hào)： TMS320M642AZDK5
廠商： Texas Instruments, Inc.
英文描述： 1A, 52kHz (250khz Max) Current Mode PWM Control Circuit with 16V UVLO Threshold and 48% Max Duty Cycle<sup>3</sup><sup>3</sup><sup>3</sup><sup>3</sup><sup>3</sup><sup>3</sup><sup>3</sup><sup>3</sup><sup>3</sup><sup>3</sup><sup>3</sup> ; Package: SOIC-8 Narrow Body; No of Pins: 8; Container: Rail; Qty per Container: 98
中文描述： 視頻/影像定點(diǎn)數(shù)字信號(hào)處理器
文件頁數(shù)： 70/123頁
文件大小： 1205K
代理商： TMS320M642AZDK5
www.ti.com
TMS320F2808, TMS320F2806
TMS320F2801, UCD9501
Digital Signal Processors
SPRS230F–OCTOBER 2003–REVISED SEPTEMBER 2005
Table 4-12. SPI-C REGISTERS
NAME
SPICCR
SPICTL
SPISTS
SPIBRR
SPIRXEMU
SPIRXBUF
SPITXBUF
SPIDAT
SPIFFTX
SPIFFRX
SPIFFCT
SPIPRI
ADDRESS
0x7760
0x7761
0x7762
0x7764
0x7766
0x7767
0x7768
0x7769
0x776A
0x776B
0x776C
0x776F
SIZE (X16)
1
1
1
1
1
1
1
1
1
1
1
1
DESCRIPTION
(1)
SPI-C Configuration Control Register
SPI-C Operation Control Register
SPI-C Status Register
SPI-C Baud Rate Register
SPI-C Receive Emulation Buffer Register
SPI-C Serial Input Buffer Register
SPI-C Serial Output Buffer Register
SPI-C Serial Data Register
SPI-C FIFO Transmit Register
SPI-C FIFO Receive Register
SPI-C FIFO Control Register
SPI-C Priority Control Register
(1)
Registers in this table are mapped to Peripheral Frame 2. This space only allows 16-bit accesses. 32-bit accesses produce undefined
results.
Table 4-13. SPI-D Registers
NAME
SPICCR
SPICTL
SPISTS
SPIBRR
SPIRXEMU
SPIRXBUF
SPITXBUF
SPIDAT
SPIFFTX
SPIFFRX
SPIFFCT
SPIPRI
ADDRESS
0x7780
0x7781
0x7782
0x7784
0x7786
0x7787
0x7788
0x7789
0x778A
0x778B
0x778C
0x778F
SIZE (X16)
1
1
1
1
1
1
1
1
1
1
1
1
DESCRIPTION
(1)
SPI-D Configuration Control Register
SPI-D Operation Control Register
SPI-D Status Register
SPI-D Baud Rate Register
SPI-D Receive Emulation Buffer Register
SPI-D Serial Input Buffer Register
SPI-D Serial Output Buffer Register
SPI-D Serial Data Register
SPI-D FIFO Transmit Register
SPI-D FIFO Receive Register
SPI-D FIFO Control Register
SPI-D Priority Control Register
(1)
Registers in this table are mapped to Peripheral Frame 2. This space only allows 16-bit accesses. 32-bit accesses produce undefined
results.
70
Peripherals
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