參數(shù)資料
型號: TMS320LC2402APAGA
英文描述: DSP|16-BIT|CMOS|TQFP|64PIN|PLASTIC
中文描述: 數(shù)字信號處理器| 16位|的CMOS | TQFP封裝| 64管腳|塑料
文件頁數(shù): 89/132頁
文件大?。?/td> 1707K
代理商: TMS320LC2402APAGA
SPRS145G
JULY 2000
REVISED FEBRUARY 2002
89
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
1443
TIMING EVENT MANAGER INTERFACE
PWM timings
PWM refers to all PWM outputs on EVA and EVB.
switching characteristics over recommended operating conditions for PWM timing
[H = 0.5t
c(CO)
] (see Figure 34)
PARAMETER
MIN
MAX
UNIT
tw(PWM)
td(PWM)CO
PWM outputs may be 100%, 0%, or increments of tc(CO) with respect to the PWM period.
Pulse duration, PWMx output high/low
2H+5
ns
Delay time, CLKOUT low to PWMx output switching
15
ns
timing requirements
[H = 0.5t
c(CO)
] (see Figure 35)
MIN
MAX
UNIT
tw(TMRDIR)
tw(TMRCLK)
twh(TMRCLK)
tc(TMRCLK)
Parameter TMRDIR is equal to the pin TDIRx, and parameter TMRCLK is equal to the pin TCLKINx.
Pulse duration, TMRDIR low/high
4H+5
ns
Pulse duration, TMRCLK low as a percentage of TMRCLK cycle time
40
60
%
Pulse duration, TMRCLK high as a percentage of TMRCLK cycle time
40
60
%
Cycle time, TMRCLK
4
tc(CO)
ns
tw(PWM)
td(PWM)CO
PWMx
CLKOUT
Figure 34. PWM Output Timing
CLKOUT
tw(TMRDIR)
TMRDIR
Parameter TMRDIR is equal to the pin TDIRx.
Figure 35. TMRDIR Timing
相關(guān)PDF資料
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