參數(shù)資料
型號： TMS320LC17
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： Digital Signal Processors(278ns指令周期，分離的程序和數(shù)據(jù)總線，外部輪詢中斷的DSP)
中文描述： 數(shù)字信號處理器（278ns指令周期，分離的程序和數(shù)據(jù)總線，外部輪詢中斷的數(shù)字信號處理器）
文件頁數(shù)： 99/139頁
文件大小： 1478K
代理商： TMS320LC17
TMS320C17, TMS320E17
DIGITAL SIGNAL PROCESSORS
SPRS009C–JANUARY 1987–REVISED JULY 1991
POST OFFICE BOX 1443
HOUSTON, TEXAS 77001
99
coprocessor port (continued)
The external processor recognizes the coprocessor interface in which both processors run asynchronously as
a memory-mapped I/O operation. The external processor lowers the WR line and places data on the bus. It next
raises the WR line to clock the data into the on-chip latch. The rising edge of WR automatically creates an
interrupt to the
′
C17/E17/P17, and the falling edge of WR clears the RBLE (receive buffer latch empty) flag.
When the
′
C17/E17/P17 reads the coprocessor port, it causes the RBLE signal to transition to a logic low state
that clears the data in the latch, and allows the interrupt condition to be cleared internally. Likewise, the external
processor reads form the latch by driving the RD line active low, thus enabling the output latch to drive the latched
data. When the data has been read, the external device will again bring the RD line high. This activates the BIO
line to signal that the transfer is complete and the latch is available for the next transfer. The falling edge of RD
resets the TBLF (transmit buffer latch full) flag. Note that the EXINT and BIO lines are reserved for coprocessor
interface and cannot be driven externally when in the coprocessor mode.
An example of the use of a coprocessor interface is shown in Figure 18, in which the
′
C17/E17/P17 are DSPs
interfaced to the TMS70C42, an 8-bit microcontroller.
MC
MC/PM
HI/LO
CLKOUT
RD
TBLF
LD7
LD6
LD5
LD4
LD3
LD2
LD1
LD0
TMS320C17/E17/P17
TMS70C42
XTAL2
A3
A2
D7
D6
D5
D4
D3
D2
D1
D0
WR
RBLE
A1
A0
17
9
8
19
20
21
22
23
24
26
27
7
6
6
32
40
19
20
21
22
23
24
25
26
31
1
3
27
2
Figure 18. Coprocessor Interface
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