參數(shù)資料
型號： TMS320LC17
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： Digital Signal Processors(278ns指令周期，分離的程序和數(shù)據(jù)總線，外部輪詢中斷的DSP)
中文描述： 數(shù)字信號處理器（278ns指令周期，分離的程序和數(shù)據(jù)總線，外部輪詢中斷的數(shù)字信號處理器）
文件頁數(shù)： 97/139頁
文件大小： 1478K
代理商： TMS320LC17
31 30 29 28 27 26 25 24 23 22
21 20 19 18
17
16 15
14 13
12 11 10
9
8
7
6
5
4
3
2
1
0
Interrupt Mask Bits
Frame Counter Modulus
FR
Pulse
Widt
h
Port 1
Port 0
Reserved
I/O
Control
Serial Clock
Prescale Control
Serial-Port Configuration
Companding Hardware Control
Interrupt Flags
Port 1 configuration control:
External framing enable:
Serial-port enable:
μ
-law/A-law encoder enable:
μ
-law/A-law decoder enable:
μ
-law/A-law decoder encode/decoded select:
0 = SCLK is an output, derived from the prescaler in timing logic.
1 = SCLK is an input that provides the clock for serial port and frame counter in timing logic.
Frame counter modulus. Controls FR frequency = SCLK/(CNT + 2) where CNT is binary value fo CR23-CR16
Serial clock control:
FR pulse-width control:
Two’s-complement
μ
-law/A-law conversion enable:
8/16-bit length coprocessor mode select:
Reserved for future expansion: Should be set to zero.
Interrupt flag is cleared by writing a logic 1 to the bit with an OUT instruction to port 0.
All ones in CR23-CR16 indicate a degenerative state and should be avoided. Bits are operational whether SCLK is an input or an output.
CNT must be greater than 7.
TMS320C17, TMS320E17, TMS320LC17, TMS320P17
DIGITAL SIGNAL PROCESSORS
SPRS009C–JANUARY 1987–REVISED JULY 1991
POST OFFICE BOX 1443
HOUSTON, TEXAS 77001
97
Table 6. Control Register Configuration
BIT
DESCRIPTION AND CONFIGURATION
0
EXINT Interrupt flag
FSR interrupt flag
FSX interrupt flag
FR interrupt flag
1
2
3
4
EXINT interrupt enable mask. When set to logic 1, an interrupt on EXINT activates device interrupt circuitry.
5
FSR interrupt enable mask. Same as EXINT control.
6
FSX interrupt enable mask. Same as EXINT control.
7
FR interrupt enable mask. Same as EXINT control.
8
0 = port 1 connects to either serial-port registers or companding hardware.
1 = port 1 accesses CR31-CR16.
0 = serial-port data transfers controlled by active FR.
1 = serial-port data transfers controlled by active FSX/FSR.
XF external logic output flag latch
9
10
11
0 = Parallel companding mode; serial port disabled.
1 = serial companding mode; serial port registers enabled.
0 = disabled.
1 = data written to port 1 is
μ
-law or A-law encoded.
0 = disabled.
1 = data written to port 1 is
μ
-law or A-law decoded.
0 = companding hardware performs
μ
-law conversion.
1 = companding hardware performs A-law conversion.
12
13
14
15
23-16
27-24
SCLK prescale cotnrol bits. (See Table 7 for divide ratios.)
28
0 = fixed-data rate; FR is 1 SCLK cycle wide.
1 = variable-data rate; FR is 8 SCLK cycles wide.
0 = sign-magnitude companding
1 = twos-complement companding
0 = 8-bit byte length
1 = 16-bit word length
29
30
31
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