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參數(shù)資料
| 型號： | TMS320FZ |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Adjustable 1.24-16V +/-0.5% Tolerance, 0.05-20mA Shunt Regulator, Pb-Free Device; Package: TO-92 (TO-226) 5.33mm Body Height; No of Pins: 3; Container: Tape and Reel; Qty per Container: 2000 |
| 中文描述： | 第二代數(shù)字信號處理器 |
| 文件頁數(shù)： | 56/123頁 |
| 文件大?。?/td> | 1205K |
| 代理商： | TMS320FZ |
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Result Registers
EPWMSOCB
S/W
GPIO/XINT2
_ADCSOC
EPWMSOCA
S/W
Sequencer 2
Sequencer 1
SOC
SOC
ADC Control Registers
70B7h
70B0h
70AFh
70A8h
Result Reg 15
Result Reg 8
Result Reg 7
Result Reg 1
Result Reg 0
Module
ADC
12-Bit
Analog
MUX
ADCINA0
ADCINA7
ADCINB0
ADCINB7
System
Control Block
High-Speed
Prescaler
HSPCLK
ADCENCLK
DSP
SYSCLKOUT
S/H
S/H
HALT
TMS320F2808, TMS320F2806
TMS320F2801, UCD9501
Digital Signal Processors
SPRS230F–OCTOBER 2003–REVISED SEPTEMBER 2005
Figure 4-7. Block Diagram of the ADC Module
To obtain the specified accuracy of the ADC, proper board layout is very critical. To the best extent
possible, traces leading to the ADCIN pins should not run in close proximity to the digital signal paths.
This is to minimize switching noise on the digital lines from getting coupled to the ADC inputs.
Furthermore, proper isolation techniques must be used to isolate the ADC module power pins ( V
DD1A18
,
V
DD2A18
, V
DDA2
, V
DDAIO
) from the digital supply.
Figure 4-8
shows the ADC pin connections for the 280x
devices.
NOTE
1. The ADC registers are accessed at the SYSCLKOUT rate. The internal timing of the
ADC module is controlled by the high-speed peripheral clock (HSPCLK).
2. The behavior of the ADC module based on the state of the ADCENCLK and HALT
signals is as follows:
–
ADCENCLK:
On reset, this signal will be low. While reset is active-low (XRS) the
clock to the register will still function. This is necessary to make sure all registers
and modes go into their default reset state. The analog module, however, will be
in a low-power inactive state. As soon as reset goes high, then the clock to the
registers will be disabled. When the user sets the ADCENCLK signal high, then
the clocks to the registers will be enabled and the analog module will be enabled.
There will be a certain time delay (ms range) before the ADC is stable and can be
used.
–
HALT:
This mode only affects the analog module. It does not affect the registers.
In this mode, the ADC module goes into low-power mode. This mode also will stop
the clock to the CPU, which will stop the HSPCLK; therefore, the ADC register
logic will be turned off indirectly.
56
Peripherals
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