參數(shù)資料
型號: TMS320FAMILY
元件分類: 數(shù)字信號處理
英文描述: 16-Bit Digital Signal Processor
中文描述: 16位數(shù)字信號處理器
文件頁數(shù): 111/132頁
文件大?。?/td> 1707K
代理商: TMS320FAMILY
SPRS145G
JULY 2000
REVISED FEBRUARY 2002
111
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
1443
internal ADC module timings
(see Figure 50)
MIN
33.3
MAX
UNIT
tc(AD)
Cycle time, ADC prescaled clock
l ti
l d l
LF240xA
LC240xA
25
ns
P l
Pulse d
conversion time
ti
t t l
l /h ld
d
For LF240xA
500
tw(SHC)
For LC2406A and LC2404A
375
ns
For LC2402A
425
tw(SH)
tw(C)
Pulse duration, sample and hold time
2tc(AD)
§
10tc(AD)
32tc(AD)
ns
Pulse duration, total conversion time
ns
td(SOC-SH)
Delay time, start of conversion to beginning
of sample and hold
2tc(CO)
ns
td(EOC)
Delay time, end of conversion to data loaded
into result register
2tc(CO)
ns
td(ADCINT)
The ADC timing diagram represents a typical conversion sequence. Refer to the ADC chapter in the
TMS320LF/LC240xA DSP Controllers
Reference Guide: System and Peripherals
(literature number SPRU357) for more details.
The total sample/hold and conversion time is determined by the summation of tw(SH), tw(C), and td(EOC).
§
Can be varied by ACQ Prescalar bits in the ADCCTRL1 register
Delay time, ADC flag to ADC interrupt
2tc(CO)
ns
0
3
2
4
5
1
tw(C)
6
7
8
tc(AD)
ADC Clock
Analog Input
Bit Converted
td(SOC
SH)
EOC/Convert
Internal Start/
Sample Hold
Start of Convert
XFR to RESULTn
tw(SHC)
á
ááááááááááááááááááááá
td(EOC)
9
tw(SH)
td(ADCINT)
ADC Interrupt
Figure 50. Analog-to-Digital Internal Module Timing
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