參數(shù)資料
型號: TMS320F2812PBKS
廠商: Texas Instruments, Inc.
英文描述: Adjustable 1.24-16V ±1% Tolerance, 0.05-20mA Shunt Regulator; Package: TSOP-5 / SOT23-5; No of Pins: 5; Container: Tape and Reel; Qty per Container: 3000
中文描述: 數(shù)字信號處理器
文件頁數(shù): 93/123頁
文件大?。?/td> 1205K
代理商: TMS320F2812PBKS
www.ti.com
OSCCLK
SYSCLKOUT
Write to PLLCR
OSCCLK * 2
(Current CPU
Frequency)
OSCCLK/2
(CPU Frequency While PLL is Stabilizing
With the Desired Frequency. This Period
(PLL Lock-up Time, t
p
) is
131072 OSCCLK Cycles Long.)
OSCCLK * 4
(Changed CPU Frequency)
6.8
General-Purpose Input/Output (GPIO)
6.8.1
GPIO - Output Timing
GPIO
t
r(GPO)
t
f(GPO)
TMS320F2808, TMS320F2806
TMS320F2801, UCD9501
Digital Signal Processors
SPRS230F–OCTOBER 2003–REVISED SEPTEMBER 2005
Figure 6-7. Example of Effect of Writing Into PLLCR Register
Table 6-12. General-Purpose Output Switching Characteristics
PARAMETER
MIN
MAX
UNIT
ns
ns
MHz
t
r(GPO)
t
f(GPO)
t
fGPO
Rise time, GPIO switching low to high
Fall time, GPIO switching high to low
Toggling frequency, GPO pins
All GPIOs
All GPIOs
8
8
25
Figure 6-8. General-Purpose Output Timing
Electrical Specifications
93
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參數(shù)描述
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