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參數(shù)資料
| 型號： | TMS320F2812PBKS |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Adjustable 1.24-16V ±1% Tolerance, 0.05-20mA Shunt Regulator; Package: TSOP-5 / SOT23-5; No of Pins: 5; Container: Tape and Reel; Qty per Container: 3000 |
| 中文描述： | 數(shù)字信號處理器 |
| 文件頁數(shù)： | 43/123頁 |
| 文件大?。?/td> | 1205K |
| 代理商： | TMS320F2812PBKS |
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TMS320F2808, TMS320F2806
TMS320F2801, UCD9501
Digital Signal Processors
SPRS230F–OCTOBER 2003–REVISED SEPTEMBER 2005
Table 3-14. PLLCR Register Bit Definitions
SYSCLKOUT
(CLKIN)
(2)
OSCCLK/2
OSCCLK
(OSCCLK*1)/2
(OSCCLK*2)/2
(OSCCLK*3)/2
(OSCCLK*4)/2
(OSCCLK*5)/2
(OSCCLK*6)/2
(OSCCLK*7)/2
(OSCCLK*8)/2
(OSCCLK*9)/2
(OSCCLK*10)/2
reserved
PLLCR[DIV]
(1)
PLLSTS[CLKINDIV]
0000 (PLL bypass)
0000 (PLL bypass)
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011-1111
0
1
0
0
0
0
0
0
0
0
0
0
0
(1)
(2)
This register is EALLOW protected.
CLKIN is the input clock to the CPU. SYSCLKOUT is the output
clock from the CPU. The frequency of SYSCLKOUT is the same as
CLKIN.
CAUTION
PLLSTS[CLKINDIV] can be set to 1 only if PLLCR is 0x0000. PLLCR should not be
changed once PLLSTS[CLKINDIV] is set.
The PLL-based clock module provides two modes of operation:
Crystal-operation - This mode allows the use of an external crystal/resonator to provide the time base
to the device.
External clock source operation - This mode allows the internal oscillator to be bypassed. The device
clocks are generated from an external clock source input on the X1 or the XCLKIN pin.
Table 3-15. Possible PLL Configuration Modes
SYSCLKOUT
(CLKIN)
OSCCLK/2
PLL MODE
REMARKS
PLLSTS[CLKINDIV]
Invoked by the user setting the PLLOFF bit in the PLLSTS register. The PLL block
is disabled in this mode. This can be useful to reduce system noise and for low
power operation. The PLLCR register must first be set to 0x0000 (PLL Bypass)
before entering this mode. The CPU clock (CLKIN) is derived directly from the
input clock on either X1/X2, X1 or XCLKIN.
PLL Bypass is the default PLL configuration upon power-up or after an external
reset (XRS). This mode is selected when the PLLCR register is set to 0x0000 or
while the PLL locks to a new frequency after the PLLCR register has been
modified. In this mode, the PLL itself is bypassed but the PLL is not turned off.
Achieved by writing a non-zero value n into the PLLCR register. Upon writing to the
PLLCR the device will switch to PLL Bypass mode until the PLL locks.
0
PLL Off
1
OSCCLK
0
OSCCLK/2
PLL Bypass
1
OSCCLK
PLL Enable
0
OSCCLK*n/2
3.6.1.3
Loss of Input Clock
In PLL-enabled and PLL-bypass mode, if the input clock OSCCLK is removed or absent, the PLL will still
issue a "limp-mode" clock. The limp-mode clock continues to clock the CPU and peripherals at a typical
frequency of 1-5 MHz. Limp mode is not specified to work from power-up, only after input clocks have
been present initially. In PLL bypass mode, the limp mode clock from the PLL is automatically routed to
the CPU if the input clock is removed or absent.
Functional Overview
43
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