tw(RSL1) th(boot-mode)(C) V (3.3 V) DDIO DDA , INTOSC1 X" />
參數(shù)資料
型號: TMS320F28069PZPQ
廠商: Texas Instruments
文件頁數(shù): 138/174頁
文件大?。?/td> 0K
描述: IC MCU 32BIT 256KB FLSH 100HTQFP
產(chǎn)品培訓(xùn)模塊: ControlSUITE
Piccolo F2806x
TPS75005 Single IC Power for C2000 MCU
標(biāo)準(zhǔn)包裝: 1,000
系列: TMS320F2806x, Piccolo™, C2000™
核心處理器: C28x
芯體尺寸: 32-位
速度: 80MHz
連通性: CAN,I²C,McBSP,SCI,SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,DMA,POR,PWM,WDT
輸入/輸出數(shù): 54
程序存儲器容量: 256KB(128K x 16)
程序存儲器類型: 閃存
RAM 容量: 50K x 16
電壓 - 電源 (Vcc/Vdd): 1.71 V ~ 1.995 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 16x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 125°C
封裝/外殼: 100-TQFP 裸露焊盤
包裝: 托盤
tw(RSL1)
th(boot-mode)(C)
V
(3.3 V)
DDIO
DDA
,
INTOSC1
X1/X2
XRS
(D)
Boot-Mode
Pins
V
(1.8 V)
DD
XCLKOUT
User-code dependent
Boot-ROM execution starts
Peripheral/GPIO function
Based on boot code
GPIO pins as input
t
OSCST
Address/Data/
Control
(Internal)
Address/data valid, internal boot-ROM code execution phase
User-code execution phase
td(EX)
t
INTOSCST
(A)
(B)
I/O Pins
GPIO pins as input (state depends on internal PU/PD)
User-code dependent
(E)
SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012
5.5
Power Sequencing
There is no power sequencing requirement needed to ensure the device is in the proper state after reset
or to prevent the I/Os from glitching during power up or power down (GPIO19, GPIO26–27, GPIO34–38
do not have glitch-free I/Os). No voltage larger than a diode drop (0.7 V) above VDDIO should be applied to
any digital pin (for analog pins, it is 0.7 V above VDDA) prior to powering up the device. Voltages applied to
pins on an unpowered device can bias internal p-n junctions in unintended ways and produce
unpredictable results.
A.
Upon power up, SYSCLKOUT is OSCCLK/4. Since the XCLKOUTDIV bits in the XCLK register come up with a reset
state of 0, SYSCLKOUT is further divided by 4 before it appears at XCLKOUT. XCLKOUT = OSCCLK/16 during this
phase.
B.
Boot ROM configures the DIVSEL bits for /1 operation. XCLKOUT = OSCCLK/4 during this phase. Note that
XCLKOUT will not be visible at the pin until explicitly configured by user code.
C.
After reset, the boot ROM code samples Boot Mode pins. Based on the status of the Boot Mode pin, the boot code
branches to destination memory or boot code function. If boot ROM code executes after power-on conditions (in
debugger environment), the boot code execution time is based on the current SYSCLKOUT speed. The SYSCLKOUT
will be based on user environment and could be with or without PLL enabled.
D.
Using the XRS pin is optional due to the on-chip power-on reset (POR) circuitry.
E.
The internal pullup or pulldown will take effect when BOR is driven high.
Figure 5-4. Power-on Reset
66
Peripheral and Electrical Specifications
Copyright 2010–2012, Texas Instruments Incorporated
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