參數(shù)資料
型號： TMS320F240PQA
英文描述： 16-Bit Microcontroller
中文描述： 16位微控制器
文件頁數(shù)： 26/105頁
文件大小： 1481K
代理商： TMS320F240PQA
TMS320C240, TMS320F240
DSP CONTROLLERS
SPRS042D – OCTOBER 1996 – REVISED NOVEMBER 1998
26
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
hardware-generated interrupts (continued)
Table 7. ’x240 Interrupt Locations and Priorities (Continued)
INTERRUPT
NAME
OVERALL
PRIORITY
DSP-CORE
INTERRUPT,
AND
ADDRESS
INT5
PERIPHERAL
VECTOR
ADDRESS
PERIPHERAL
VECTOR
ADDRESS
OFFSET
0005h
MASKABLE
’x240
SOURCE
PERIPHERAL
MODULE
SPI
FUNCTION
INTERRUPT
SPIINT
34
SYSIVR
(701Eh)
Y
Low-priority SPI interrupt
RXINT
35
000Ah
(System)
0006h
Y
SCI
SCI receiver interrupt
(low priority)
TXINT
36
0007h
Y
SCI
SCI transmitter interrupt
(low priority)
ADCINT
37
INT6
SYSIVR
0004h
Y
ADC
Analog-to-digital interrupt
XINT1
XINT2
XINT3
38
39
40
000Ch
(System)
(701Eh)
0001h
0011h
001Fh
Y
Y
Y
External
pins
Low-priority external
user interrupts
RESERVED
41
000Eh
N/A
Y
DSP Core
Used for analysis
TRAP
N/A
0022h
N/A
N/A
TRAP instruction vector
external interrupts
The ’x240 has five external interrupts. These interrupts include:
XINT1.
Type A interrupt. The XINT1 control register (at 7070h) provides control and status for this interrupt.
XINT1 can be used as a high-priority (Level 1) or low-priority (Level 6) maskable interrupt or as a
general-purpose input pin. XINT1 can also be programmed to trigger an interrupt on either the rising or the
falling edge.
NMI.
Type A interrupt. The NMI control register (at 7072h) provides control and status for this interrupt. NMI
is a nonmaskable external interrupt or a general-purpose input pin. NMI can also be programmed to trigger
an interrupt on either the rising or the falling edge.
XINT2.
Type C interrupt. The XINT2 control register (at 7078h) provides control and status for this interrupt.
XINT2 can be used as a high-priority (Level 1) or low-priority (Level 6) maskable interrupt or a
general-purpose I/O pin. XINT2 can also be programmed to trigger an interrupt on either the rising or the
falling edge.
XINT3.
Type C interrupt. The XINT3 control register (at 707Ah) provides control and status for this interrupt.
XINT3 can be used as a high-priority (Level 1) or low-priority (Level 6) maskable interrupt or as a
general-purpose I/O pin. XINT3 can also be programmed to trigger an interrupt on either the rising or the
falling edge.
PDPINT.
This interrupt is provided for safe operation of the power converter and motor drive. This maskable
interrupt can put the timers and PWM output pins in the high-impedance state and inform the CPU in case
of motor drive abnormalities such as overvoltage, overcurrent, and excessive temperature rise. PDPINT is
a Level 2 interrupt.
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