參數(shù)資料
型號： TMS320F206PZL
元件分類： 數(shù)字信號處理
英文描述： 16-Bit Digital Signal Processor
中文描述： 16位數(shù)字信號處理器
文件頁數(shù)： 20/57頁
文件大小： 793K
代理商： TMS320F206PZL
TMS320F206
DIGITAL SIGNAL PROCESSOR
SPRS050A – NOVEMBER 1996 – REVISED APRIL 1998
20
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
on-chip registers (continued)
Table 8. On-Chip Memory and I/O Mapped Registers (Continued)
NAME
ADDRESS
VALUE AT
RESET
DESCRIPTION
ICR
IS@FFEC
0000h
Interrupt control register. This register is used to determine which interrupt is active since
INT1 and HOLD share an interrupt vector as do INT2 and INT3. A portion of this register is
for mask/unmask (similar to IFR). At reset, all bits are zeroed, thereby allowing the HOLD
mode to be enabled. The MODE bit is used by the hold-generating circuit to determine if a
HOLD or INT1 is active.
SDTR
IS@FFF0
xxxxh
Synchronous serial port (SSP) transmit and receive register
SSPCR
IS@FFF1
0030h
Synchronous serial-port control register. This register controls serial-port operation as
defined by the register bits.
SSPST
IS@FFF2
0000h
Synchronous serial-port status register
SSPMC
IS@FFF3
0000h
Synchronous serial-port multichannel register
ADTR
IS@FFF4
xxxxh
Asynchronous serial port (ASP) transmit and receive register
ASPCR
IS@FFF5
0000h
Asynchronous serial-port control register (ASPCR). This register controls the asynchronous
serial-port operation.
IOSR
IS@FFF6
18xxh
I/O status register. IOSR is used for detecting current levels (and changes when inputs) on
pins IO0–IO3 and status of UART.
BRD
IS@FFF7
0001h
Baud-rate divisor register (baud-rate generator). 16-bit register used to determine baud rate
of UART. No data is transmitted/received if BRD is zero.
TCR
IS@FFF8
0000h
Timer-control register. This 10-bit register contains the control bits that define the
divide-down ratio, start/stop the timer, and reload the period. Also contained in this register
is the current count in the prescaler. Reset initializes the timer divide-down ratio to 0 and
starts the timer.
PRD
IS@FFF9
FFFFh
Timer-period register. This 16-bit register contains the 16-bit period that is loaded into the
timer counter when the counter borrows or when the reload bit is activated. Reset initializes
the PRD to 0xFFFF.
TIM
IS@FFFA
FFFFh
Timer-counter register. This 16-bit register contains the current 16-bit count of the timer.
Reset initializes the TIM to 0xFFFF.
SSPCT
IS@FFFB
0000h
Synchronous serial-port counter register
WSGR
IS@FFFC
0FFFh
Wait-state generator register. This register contains 12 control bits to enable 0 to 7 wait
states to program, data, and I/O space. Reset initializes WSGR to 0x0FFFh.
‘x’ indicates undefined or value based on the pin levels at reset.
external interface
The TMS320F206 can address up to 64K
×
16 words of memory or registers in each of the program, data, and
I/O spaces. On-chip memory, when enabled, occupies some of this off-chip range. In data space, the high
32K words can be mapped dynamically either locally or globally using the GREG register as described in the
TMS320C2xx User’s Guide(literature number SPRU127). A data-memory access that is mapped as global
asserts BR low (with timing similar to the address bus).
The CPU of the TMS320F206 schedules a program fetch, data read, and data write on the same machine cycle.
This is because from on-chip memory, the CPU can execute all three of these operations in the same cycle.
However, the external interface multiplexes the internal buses to one address and one data bus. The external
interface sequences these operations to complete first the data write, then the data read, and finally the program
read.
The ’F206 supports a wide range of system interfacing requirements. Program, data, and I/O address spaces
provide interface to memory and I/O, thereby maximizing system throughput. The full 16-bit address and data
bus, along with the PS, DS, and IS space-select signals, allow addressing of 64K 16-bit words in each of the
three spaces.
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