參數(shù)資料
型號： TMS320C6727BGDH275
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： Floating-Point Digital Signal Processors
中文描述： 浮點數(shù)字信號處理器
文件頁數(shù)： 104/114頁
文件大小： 1030K
代理商： TMS320C6727BGDH275
www.ti.com
BOARD
DV
DD
(3.3 V)
EMI
Filter
10 F
0.1 F
PLLHV
Place Filter and Capacitors as Close
to DSP as Possible
EMI Filter: TDK ACF451832333, 223, 153, or 103,
Panasonic EXCCET103U, or Equivalent
+
TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720
Floating-Point Digital Signal Processors
SPRS370–SEPTEMBER 2006
Table 4-42. Allowed PLL Operating Conditions
ALLOWED SETTING OR RANGE
MIN
125 ns
187.5 μs
PARAMETER
DEFAULT VALUE
MAX
1
2
PLLRST = 1 assertion time during initialization
Lock time before setting PLLEN = 1. After changing D0, PLLM, or
input clock.
PLL input frequency (PLLREF after D0
(1)
)
PLL multiplier values (PLLM)
PLL output frequency (PLLOUT before dividers D1, D2, D3)
(2)
SYSCLK1 frequency (set by PLLM and dividers D0, D1)
N/A
N/A
3
4
5
6
12 MHz
x4
140 MHz
50 MHz
x25
600 MHz
x13
N/A
PLLOUT/1
Device Frequency
Specification
7
8
SYSCLK2 frequency (set by PLLM and dividers D0, D2)
SYSCLK3 frequency (set by PLLM and dividers D0, D3)
PLLOUT/2
PLLOUT/3
/2, /3, or /4 of SYSCLK1
EMIF Frequency
Specification
(1)
(2)
Some values for the D0 divider produce results outside of this range and should not be selected.
In general, selecting the PLL output clock rate closest to the maximum frequency will decrease clock jitter.
CAUTION
SYSCLK1, SYSCLK2, SYSCLK3 must be configured as aligned by setting ALNCTL[2:0]
to '1'; and the PLLCMD.GOSET bit must be written every time the dividers D1, D2, and
D3 are changed in order to make sure the change takes effect and preserves
alignment.
CAUTION
When changing the PLL parameters which affect the SYSCLK1, SYSCLK2, SYSCLK3
dividers, the bridge BR2 in
Figure 2-4
must be reset by the CFGBRIDGE register. See
Table 2-7
.
The PLL is an analog circuit and is sensitive to power supply noise. Therefore it has a dedicated 3.3-V
power pin (PLLHV) that should be connected to DV
DD
at the board level through an external filter, as
illustrated in
Figure 4-44
.
Figure 4-44. PLL Power Supply Filter
104
Peripheral and Electrical Specifications
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TMS320C6727BGDH300 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC Floating-Point DSP RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
TMS320C6727BGDH350 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC Floating-Point DSP RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
TMS320C6727BZDH250 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC Floating-Pt Dig RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
TMS320C6727BZDH275 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC Floating-Point DSP RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
TMS320C6727BZDH300 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC Floating-Point DSP RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
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