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      參數(shù)資料
      型號(hào): TMS320C6211GGP167
      廠商: Texas Instruments, Inc.
      元件分類: 數(shù)字信號(hào)處理
      英文描述: FIXED-POINT DIGITAL SIGNAL PROCESSORS
      中文描述: 定點(diǎn)數(shù)字信號(hào)處理器
      文件頁數(shù): 42/123頁
      文件大小: 1205K
      代理商: TMS320C6211GGP167
      www.ti.com
      External Clock Signal
      (Toggling 0V
      DDIO
      )
      XCLKIN
      X2
      NC
      X1
      External Clock Signal
      (Toggling 0V
      DD
      )
      XCLKIN
      X2
      NC
      X1
      C
      L1
      X2
      X1
      Crystal
      C
      L2
      XCLKIN
      TMS320F2808, TMS320F2806
      TMS320F2801, UCD9501
      Digital Signal Processors
      SPRS230F–OCTOBER 2003–REVISED SEPTEMBER 2005
      2. A 1.8-V external oscillator can be directly connected to the X1 pin. The X2 pin should be left
      unconnected and the XCLKIN pin tied low. The logic-high level in this case should not exceed V
      DD
      .
      The three possible input-clock configurations are shown in
      Figure 3-9
      through
      Figure 3-11
      Figure 3-9. Using a 3.3-V External Oscillator
      Figure 3-10. Using a 1.8-V External Oscillator
      Figure 3-11. Using the Internal Oscillator
      3.6.1.1
      External Reference Oscillator Clock Option
      The typical specifications for the external quartz crystal for a frequency of 20 MHz are listed below:
      Fundamental mode, parallel resonant
      C
      L
      (load capacitance) = 12 pF
      C
      L1
      = C
      L2
      = 24 pF
      C
      shunt
      = 6 pF
      ESR range = 30 to 60
      TI recommends that customers have the resonator/crystal vendor characterize the operation of their
      device with the DSP chip. The resonator/crystal vendor has the equipment and expertise to tune the tank
      circuit. The vendor can also advise the customer regarding the proper tank component values that will
      produce proper start up and stability over the entire operating range.
      3.6.1.2
      PLL-Based Clock Module
      The 280x devices have an on-chip, PLL-based clock module. This module provides all the necessary
      clocking signals for the device, as well as control for low-power mode entry. The PLL has a 4-bit ratio
      control PLLCR[DIV] to select different CPU clock rates. The watchdog module should be disabled before
      writing to the PLLCR register. It can be re-enabled (if need be) after the PLL module has stabilized, which
      takes 131072 OSCCLK cycles.
      Functional Overview
      42
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