參數(shù)資料
型號: TMS320C6203CGNZ300
英文描述: DSP|32-BIT|CMOS|BGA|352PIN|PLASTIC
中文描述: 數(shù)字信號處理器| 32位|的CMOS | BGA封裝| 352PIN |塑料
文件頁數(shù): 91/132頁
文件大小: 1707K
代理商: TMS320C6203CGNZ300
SPRS145G
JULY 2000
REVISED FEBRUARY 2002
91
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
1443
interrupt timings
INT refers to XINT1 and XINT2. PDP refers to PDPINTx.
switching characteristics over recommended operating conditions (see Figure 37)
PARAMETER
MIN
MAX
UNIT
td(PDP-PWM)HZ
Delay time, PDPINTx low to PWM high-impedance state
12
ns
td(INT)
Delay time, INT low/high to interrupt-vector fetch
10tc(CO)
ns
timing requirements (see Figure 37)
MIN
MAX
UNIT
t(INT)
Pulse duration INT input low/high
Pulse duration, INT input low/high
if bit 6 of SCSR2 = 0
6tc(CO)
12tc(CO)
6tc(CO)
12tc(CO)
ns
tw(INT)
if bit 6 of SCSR2 = 1
t(PDP)
Pulse duration PDPINTx input low
Pulse duration, PDPINTx input low
if bit 6 of SCSR2 = 0
ns
tw(PDP)
if bit 6 of SCSR2 = 1
This is different from 240x devices.
PWM
PDPINTx
CLKOUT
tw(PDP)
td(PDP-PWM)HZ
XINT1, XINT2
tw(INT)
Interrupt Vector
td(INT)
PWM refers to
all
the PWM pins in the device (i.e., PWMn and TnPWM pins). The state of the PWM pins after PDPINTx is taken
high depends on the state of the FCOMPOE bit.
A0
A15
Figure 37. External Interrupts Timing
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