參數(shù)資料
型號: TMS320C6203BGLS300
英文描述: DSP|32-BIT|CMOS|BGA|384PIN|PLASTIC
中文描述: 數(shù)字信號處理器| 32位|的CMOS | BGA封裝| 384PIN |塑料
文件頁數(shù): 106/132頁
文件大?。?/td> 1707K
代理商: TMS320C6203BGLS300
SPRS145G
JULY 2000
REVISED FEBRUARY 2002
106
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
1443
external memory interface
ready-on-read
timings (continued)
timing requirements for an external memory interface ready-on-read with one software wait state
and one external wait state (see Figure 47)
MIN
MAX
UNIT
th(RDY)COH
Hold time, READY after CLKOUT high
H
2.5
ns
tsu(RDY)COH
Setup time, READY before CLKOUT high
H
9.5
ns
td(COL-A)RD
Delay time, CLKOUT low to address valid
8
ns
PS, DS, IS
RD
READY
SW = 1 cycle
EXW = 1 cycle
Read Cycle
th(RDY)COH
tsu(RDY)COH
CLKOUT
R/W
W/R
D[0:15]
STRB
A[0:15]
td(COL-A)RD
Figure 47. Ready-on-Read Timings With One Software Wait (SW) State and
One External Wait (EXW) State
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