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參數(shù)資料
| 型號： | TMS28F512A-15C3FME |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | GT 26C 26#16 SKT PLUG |
| 中文描述： | 65536 8位快閃記憶體 |
| 文件頁數(shù)： | 8/21頁 |
| 文件大?。?/td> | 311K |
| 代理商： | TMS28F512A-15C3FME |
Apply VPPL
Last
Address
Start
Address = 00h
VCC = 5 V
±
10%, VPP = 12 V
±
5%
Device Passed
Increment
Address
Read
and Verify
Byte
Pass
No
Yes
Yes
No
Fail
X = 1
Command
Write Data
X = X + 1
Wait = 10
μ
s
Write Read Command
X = 25
Setup
Write Set-Up-Program
Wait = 6
μ
s
Write Program-Verify Command
Device Failed
Power
Down
Interactive
Mode
Apply VPPL
TMS28F512A
65536 BY 8-BIT
FLASH MEMORY
SMJS514C – FEBRUARY 1994 – REVISED AUGUST 1997
8
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
Bus
Operation
Command
Comments
Initialize
Address
Standby
Wait for VPP to ramp to
VPPH (see Note A)
Initialize pulse count
Write
Set-Up-Pr
ogram
Data = 40h
Write
Write Data
Valid address/data
Standby
Wait = 10
μ
s
Write
Program-
Verify
Data = C0h; ends
program operation
Standby
Wait = 6
μ
s
Read byte to verify
programming; compare
output to expected output
Read
Write
Read
Data = 00h; resets register
for read operations
Standby
Wait for VPP to ramp to
VPPL (see Note B)
NOTES: A. Refer to the recommended operating conditions for the value of VPPH.
B. Refer to the recommended operating conditions for the value of VPPL.
Figure 1. Programming Flowchart: Fastwrite Algorithm
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