參數(shù)資料
型號(hào)： TMS279X
廠商： Texas Instruments, Inc.
英文描述： FLOPPY DISK FORMATTERICONTROLLER FAMILY
中文描述： 軟盤驅(qū)動(dòng)FORMATTERICONTROLLER家庭
文件頁(yè)數(shù)： 12/40頁(yè)
文件大?。?/td> 334K
代理商： TMS279X
TMS279X (WD279X) FLOPPY DISK FORMATTER / CONTROLLER FAMILY
12
A 2 μs (MFM) or 4 μs (FM) pulse is provided as an output to the drive. For every step pulse issued, the drive
moves one track location in a direction determined by the direction output. The chip will step the drive in the
same direction it last stepped unless the command changes the direction.
The direction signal is active high when stepping in and low when stepping out. The direction signal is valid
before the first stepping pulse is generated.
The rates (shown in Table 3) can be applied to a step-direction motor through the device interface.
TABLE 3 - STEPPING RATES
CLK
2 MHz
TEST# = 1
3 ms
6 ms
10 ms
15 ms
1 MHz
TEST# = 1
6 ms
12 ms
20 ms
30 ms
r1
0
0
1
1
r0
0
1
0
1
After the last directional step, an additional 15 milliseconds of head settling time takes place if the verify flag
is set in Type I commands. Note that this time doubles to 30 ms for a 1 MHz clock. There is also a 15 ms
head settling time if the E flag is set in any Type 11 or III command.
When a Seek, Step or Restore command is executed, an optional verification of read-write head position can
be performed by setting bit 2 (V = 1) in the command word to a logic 1. The verification operation begins at
the end of the 15 millisecond settling time after the head is loaded against the media. The track number from
the first encountered ID field is compared against the contents of the track register. If the track numbers
compare and the ID field cyclic redundancy check (CRC) is correct, the verify operation is complete and an
INTRQ is generated with no errors. If there is a match but not a valid CRC, the CRC error status bit is set
(status bit 3), and the next encountered ID field is read from the disk for the verification operation.
The TMS279X must find an ID field with correct track number and correct CRC within 5 revolutions of the
media; otherwise the seek error is set and an INTRQ is generated. If V = 0, no verification is performed.
The head load (HLD) output controls the movement of the read/write head against the media. HLD is
activated at the beginning of a Type I command if the h flag is set (h = 1), at the end of the Type I command
if the verify flag (V = 1), or upon receipt of any Type II or
III command. Once HLD is active it remains active
until either a Type I command is received with (h = 0 and V = 0); or if the 279X is in an idle state (non-busy)
and 15 index pulses have occurred.
Head load timing (HLT) is an input to the 279X which is used for the head engage time. When HLT = 1, the
279X assumes the head is completely engaged. The head engage time is typically 30 to 100 ms depending
on drive. The low-to-high transition on HLD is typically used to fire a one shot. The output of the one shot is
then used for HLT and supplied as an input to the 279X
.
HLT (FROM ONE SHOT)
HEAD LOAD TIMING
相關(guān)PDF資料
PDF描述
TMS279XN FLOPPY DISK FORMATTERICONTROLLER FAMILY
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TMS279XN 制造商:TI 制造商全稱:Texas Instruments 功能描述:FLOPPY DISK FORMATTERICONTROLLER FAMILY
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TMS27C/PC256-12 制造商:TI 制造商全稱:Texas Instruments 功能描述:TMS27C256 32768 BY 8-BIT UV ERASABLE TMS27PC256 32768 BY 8-BIT PROGRAMMABLE READ-ONLY MEMORIES
TMS27C/PC256-15 制造商:TI 制造商全稱:Texas Instruments 功能描述:TMS27C256 32768 BY 8-BIT UV ERASABLE TMS27PC256 32768 BY 8-BIT PROGRAMMABLE READ-ONLY MEMORIES
TMS27C/PC256-17 制造商:TI 制造商全稱:Texas Instruments 功能描述:TMS27C256 32768 BY 8-BIT UV ERASABLE TMS27PC256 32768 BY 8-BIT PROGRAMMABLE READ-ONLY MEMORIES
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