參數(shù)資料
型號(hào)： TMPR3907F
廠商： Toshiba Corporation
英文描述： 32 Bit TX39 Family System RISC Microprocessor(32位TX39系列簡(jiǎn)化指令系統(tǒng)計(jì)算機(jī)微處理器)
中文描述： 32位TX39家庭系統(tǒng)RISC微處理器（32位TX39系列簡(jiǎn)化指令系統(tǒng)計(jì)算機(jī)微處理器）
文件頁(yè)數(shù)： 7/30頁(yè)
文件大?。?/td> 246K
代理商： TMPR3907F
1998-07-01 7/29
TMPR3907F
TENTATIVE
PCI interface signals
PCIAD[31:0]
I/O
PCI address and data
Address and data multiplex bus.
CBE[3:0]*
I/O
Bus command and byte enable
Command and byte enable signal.
PAR
I/O
Parity
Parity signal for PCIAD[31:0] and CBE[3:0].
FRAME*
I/O
Cycle frame
Indicates that a bus operation is in progress.
IRDY*
I/O
Initiator ready
Indicates that the initiator is ready to complete the data transfer.
TRDY*
I/O
Target ready
Indicates that the target is ready to complete the data transfer.
STOP*
I/O
Stop
Used by the target to request the initiator to halt the data transfer.
IDSEL
I
Initialization device select
Chip select signal used at configuration access.
DEVSEL*
I/O
Device select
Response signal used by the target to assert access from the initiator.
REQ[2:0]*
I
Request
Signal used by the master to request bus mastership.
GNT[2:0]*
O
Grant
Indicates that bus mastership is granted to the master.
PERR*
I
Parity Error
Indicates that data parity error occurred in a bus cycle other than a special cycle.
SERR*
I
System Error
Indicates data parity error in a special cycle, address parity error, or a fatal error.
PCICLK
I/O
PCI Clock
PCI bus clock. Two modes are supported: output from the TX3907 PCI controller or
input to the TX3907 PCI controller from an external source. The mode is determined by
the ROMA[21] signal state on the RESET* signal rising edge.
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