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參數(shù)資料
| 型號： | TMPR3907F |
| 廠商： | Toshiba Corporation |
| 英文描述： | 32 Bit TX39 Family System RISC Microprocessor(32位TX39系列簡化指令系統(tǒng)計算機微處理器) |
| 中文描述： | 32位TX39家庭系統(tǒng)RISC微處理器（32位TX39系列簡化指令系統(tǒng)計算機微處理器） |
| 文件頁數(shù)： | 5/30頁 |
| 文件大小： | 246K |
| 代理商： | TMPR3907F |
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1998-07-01 5/29
TMPR3907F
TENTATIVE
4.2
PIN FUNCTIONS
Signal Name
I/O
Function
System interface signals
SYSCLK
O
System clock
Outputs the same clock as that of the TX39/H core (Full-Speed Bus mode) or half the
clock of the TX39/H core (Half-Speed Bus mode). Output can be halted using the
ROMA[20] pin at a reset.
CASBE[3:0]*
O
CAS / Byte Enable
Indicates the position of the valid data on the data bus D[31:0]. Operates as a CAS*
signal at DRAM access (including refresh cycle). In 16-bit Bus mode, CASBE[1:0]* only
is used.
The following shows the correspondence between CASBE[3:0] and the data bus.
CASBE[3]* D[31:24]
CASBE[2]* D[23:16]
CASBE[1]* D[15:8]
CASBE[0]* D[7:0]
D[31:0]
I/O
Data
Data bus.
In 16-bit Bus mode, D[15:0] is used.
LAST*/RD*
O
Last/Read
In Full-Speed Bus mode, functions as the LAST* signal, which indicates the end of bus
operation. In Half-Speed Bus mode, functions as the RD* signal, which indicates that the
bus operation in progress is a read.
WR*
O
Write
Indicates that the bus operation in progress is a write.
ACK*
I/O
Acknowledge
In Full-Speed Bus mode, functions as an output signal which indicates the completion of
the bus operation. In Half-Speed mode, operates as an input signal which completes the
SCS operation.
RESET*
I
Reset
Holding this signal low for at least 60 system clocks initializes the TX3907. The TX3907
is initialized in accordance with the ROMA[23:9] setting at a RESET* signal rising edge.
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相關代理商/技術參數(shù) |
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| TMPR3911 | 制造商:TOSHIBA 制造商全稱:Toshiba Semiconductor 功能描述:32-Bit TX System RISC TX39 Family |
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