參數(shù)資料
型號(hào): TMP93CS40
英文描述: Microcontroller
中文描述: 微控制器
文件頁數(shù): 15/16頁
文件大?。?/td> 131K
代理商: TMP93CS40
TMP93CF76/CF77/CW76/CU76/CT76
2001-09-07
93CF76-187
(2) Master SCL output timing
The I2CCR1 <SCK 2:0> are used to select a maximum transfer frequency directed
from the SCL pin in the master mode.When rising time of the output clock (t
RC
) is at
least 8/fc [s], a high-level time of the output clock (t
HC
) is t
SCL
.
While the SCL line is fixed to low-level by a slave device,the output clock stops.
The first clock (t
HC
[s] ) after restart is (t
SCL
/2)
t
HC
t
SCL
.
(a) In case of t
RC
<
(8/fc) [s]
t
HC
=
t
LC
=
t
SCL
/2 [s]
(t
SCL
=
1/f
SCL
[s] )
(b)
In case of t
RC
(8/fc) [s] t
HC
=
t
SCL
[s] , t
LC
=
t
SCL
/2 [s]
SCL pin
(Output)
1/F
SCL
[s]
t
HC
t
LC
t
RC
F
SCL
=
f
SCL
0.5V
CC
SCL pin
(Output)
1/F
SCL
[s]
F
SCL
=
f
SCL
/1.5
t
RC
0.5 V
CC
t
HC
t
LC
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