TMP93CF76/CF77/CW76/CU76/CT76
2001-09-07
93CF76-186
4.4
Serial Bus Interface Timing
(1) I
2
C bus Logic Timing
Parameter
Symbol
Min
Typ.
Max
Unit
SCL cycle
SCL low pulse width
SCL High pulse width
SDA Rising Time
SDA Falling Time
SCL Rising Time
SCL Falling Time
The time from start command write to start sheecense
Start condition hold time, start generation of the first clock after this
Delay time from SCL falling to data output
Set up time of data output for SCL rising
The time of holding data for SCL rising
The time from stop command write to starting stop sheecense
The time from SDA falling to SCL rising (during stop sheecense)
Stop condition set up time
t
CYCSCL
t
LOW
t
HIGH
t
RSDA
t
FSDA
t
RSCL
t
FSCL
t
GSTA1
t
GSTA2
t
ODAT1
t
SUODAT
t
HODAT
t
GSTP1
t
GSTP2
t
GSTP3
2
N
/fc
2
N-1
/fc
0
4/fc
2
N-2
/fc
2
N-1
/fc
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
2
N-1
/fc
2
N-1
/fc
(Note 1)
(Note 1)
(Note 1)
(Note 1)
2
N
/fc
(Note 2)
(Note 2)
(Note 3)
5/fc
2
N-1
/fc
Note 1:The time of rising/falling depend on the feature of bus interface.
Note 2:The worst case is at the first bit of slave address.
Note 3:The worst case is at the acknowledge bit.
Note 4:N: dividing value set by I2CCR1 <SCK 2:0>.
SCK
N
000
001
010
011
100
101
110
111
6
7
8
9
10
11
12
reserved
t
FSDA
t
RSDA
t
GSDA2
t
SUODAT
t
HDODAT
t
HIGH
t
LOW
t
ODAT1
t
GSTA1
t
RSCL
t
FSCL
t
GSTP2
t
GSTP1
t
GSTP3
SDA
SCL
Start Command
Stop Command
t
CYCSCL
