![](http://datasheet.mmic.net.cn/260000/TMP93CF76_datasheet_15974392/TMP93CF76_9.png)
TMP93CF76/CF77/CW76/CU76/CT76
93CF76-9
2001-09-07
3.
Operation
This
TMP93CF76/CF77/CW76/CU76/CT76 devices.
section
describes
the
functions
and
basic
operational
blocks
of
See the “7. Points of Concern and Restrictions” for the using notice and restrictions for each
block.
3.1
CPU
TMP93CF76/CF77/CW76/CU76/CT76 devices have a built-in high-performance 16-bit CPU
(900/L CPU). (For CPU operation, see TLCS-900/L CPU in the previous section).
This section describes CPU functions unique to the TMP93CF76/CF77/CW76/CU76/CT76
that are not described in the previous section.
3.1.1
Reset
To reset the TMP93CF76/CF77/CW76/CU76/CT76, the RESET input must be kept at 0
for at least 10 system clocks. (1.25 μs at 16 MHz) within the operating voltage range and
with a stable oscillation.
When reset is accepted, the CPU sets as follows:
Program Counter (PC) according to Reset Vector that is stored FFFF00H to
FFFF02H.
←
stored data in location FFFF00H
PC (15:8)
←
stored data in location FFFF01H
PC (23:16)
←
stored data in location FFFF02H
Stack pointer (XSP) for system mode to 100H.
IFF2 to 0 bits of status register to 111. (Sets mask register to interrupt level 7.)
MAX bit of status register to 1. (Sets to maximum mode)
Bits RFP2 to 0 of status register to 000. (Sets register banks to 0.)
PC (7:0)
When reset is released, instruction execution starts from PC (reset vector). CPU
internal registers other than the above are not changed.
When reset is accepted, processing for built-in I/Os, ports, and other pins is as follows
Initializes built-in I/O registers as per specifications.
Sets port pins (including pins also used as built-in I/Os) to general-purpose
input/output port mode.
Note:
By resetting, register in the CPU except program counter (PC), status register
(SR) and stack pointer (XSP) and the data in internal RAM are not changed.