參數(shù)資料
型號(hào)： TMP90C400
廠商： Toshiba Corporation
元件分類： 通用總線功能
英文描述： High Speed Advanced CMOS 8-bit Microcontroller,Integrating 8-Bit CPU,RAM，ROM，General Serial Interface,Multifunction Timer/Event Counter(高速、先進(jìn)的 CMOS 8位微控制器（芯片集成了8位CPU,ROM，RAM，通用串行接口，多功能定時(shí)器/事件計(jì)數(shù)器）)
中文描述： 采用先進(jìn)的CMOS高速8位微控制器，集成8位CPU，內(nèi)存，光盤，通用串行接口，多功能定時(shí)器/事件計(jì)數(shù)器（高速，先進(jìn)的的CMOS 8位微控制器（芯片集成了8位的CPU，ROM和RAM內(nèi)存，通用串行接口，多功能定時(shí)器/事件計(jì)數(shù)器））
文件頁(yè)數(shù)： 83/100頁(yè)
文件大?。?/td> 2591K
代理商： TMP90C400
TOSHIBA CORPORATION
83
TMP90C400/401
Protocol
Select the 9-bit UART mode for the master and slave
controllers.
Set the SCMOD <WU> bit of each slave controller to
“1” to enable data receiving.
The master controller transmits 1-frame data including
the 8-bit select code for the slave controllers. The
MSB (8-bit) SCMOD <TB8> is set to “1”.
Each slave controller receives the above frame, and
clears the <WU> bit to “0” if the above select code
matches its own select code.
The master controller transmits data to the specified
slave controller (whose <WU> bit is cleared to “0”)
while setting the MSB (bit 8) <TB8> to “0”.
The slave controllers (with the SCMOD <WU> bit
remaining at “1”) ignore the receive data since the
MSB (SCCR <RB8>) are set to “0” to disable the inter-
rupt INTRX.
When the <WU> bit is cleared to “0”, the interrupt
INTRX is generated and receive data are read.
The slave controllers (WU = 0) transmits data to the
master controller. It is possible that the the master
controller to be indicated the end of data received by
this transmit data.
Example: Link two slave controllers serially with the
master controller, and use the internal clock
1 (fc/2) as the transfer clock.
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