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TOSHIBA CORPORATION
TMP90C400/401
3.4.1 RUN Mode
Figure 3.4 (2) shows the timing for releasing the HALT state by
interrupts in the RUN/IDLE 2 mode.
In the RUN mode, the system clock in the MCU continues
to operate even after a HALT instruction is executed. Only the
CPU stops executing the instruction. Until the halt state is
released, the CPU repeats dummy cycles. In the halt state, an
interrupt request is sampled with the rising edge of the CLK
signal
Figure 3.4 (2). Timing Chart for Releasing the Halt State by Interrupts in RUN/IDLE 2 Modes