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TMS470R1B768
16/32-Bit RISC Flash Microcontroller
SPNS108A–AUGUST 2005–REVISED AUGUST 2006
The B768 device has ten communication interfaces: five SPIs, two SCIs, and three HECCs. The SPI provides a
convenient method of serial interaction for high-speed communications between similar shift-register type
devices. The SCI is a full-duplex, serial I/O interface intended for asynchronous communication between the
CPU and other peripherals using the standard Non-Return-to-Zero (NRZ) format. The HECC uses a serial,
multimaster communication protocol that efficiently
communication rates of up to 1 megabit per second (Mbps). The HECC is ideal for applications operating in
noisy and harsh environments (e.g., industrial fields) that require reliable serial communication or multiplexed
wiring. For more detailed functional information on the SPI, SCI, and HECC, see the specific reference guides
for these modules (literature numbers SPNU195, SPNU196, and SPNU197, respectively).
supports
distributed
real-time
control
with
robust
The HET is an advanced intelligent timer that provides sophisticated timing functions for real-time applications.
The timer is software-controlled, using a reduced instruction set, with a specialized timer micromachine and an
attached I/O port. The HET can be used for compare, capture, or general-purpose I/O. It is especially well suited
for applications requiring multiple sensor information and drive actuators with complex and accurate time pulses.
For more detailed functional information on the HET, see the
TMS470R1x High-End Timer (HET) Reference
Guide
(literature number SPNU199).
The B768 HET peripheral contains the XOR-share feature. This feature allows two adjacent HET high-resolution
channels to be XORed together, making it possible to output smaller pulses than a standard HET. For more
detailed information on the HET XOR-share feature, see the
TMS470R1x High-End Timer (HET) Reference
Guide
(literature number SPNU199).
The B768 device has a 10-bit-resolution, 16-channel sample-and-hold MibADC. The MibADC channels can be
converted individually or can be grouped by software for sequential conversion sequences. There are three
separate groupings, two of which are triggerable by an external event. Each sequence can be converted once
when triggered or configured for continuous conversion mode. For more detailed functional information on the
MibADC, see the
TMS470R1x Multi-Buffered Analog-to-Digital Converter (MibADC) Reference Guide
(literature
number SPNU206).
The zero-pin phase-locked loop (ZPLL) clock module contains a phase-locked loop, a clock-monitor circuit, a
clock-enable circuit, and a prescaler (with prescale values of 1–8). The function of the ZPLL is to multiply the
external frequency reference to a higher frequency for internal use. The ZPLL provides ACLK to the system
(SYS) module. The SYS module subsequently provides system clock (SYSCLK), real-time interrupt clock
(RTICLK), CPU clock (MCLK), and peripheral interface clock (ICLK) to all other B768 device modules. For more
detailed functional information on the ZPLL, see the
TMS470R1x Zero-Pin Phase-Locked Loop (ZPLL) Clock
Module Reference Guide
(literature number SPNU212).
NOTE:
ACLK should not be confused with the MibADC internal clock, ADCLK. ACLK is the
continuous system clock from an external resonator/crystal reference.
The B768 device also has an external clock prescaler (ECP) module that when enabled, outputs a continuous
external clock (ECLK) on a specified GIO pin. The ECLK frequency is a user-programmable ratio of the
peripheral interface clock (ICLK) frequency. For more detailed functional information on the ECP, see the
TMS470R1x External Clock Prescaler (ECP) Reference Guide
(literature number SPNU202).
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