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參數(shù)資料
| 型號(hào)： | TMP401AIDGKTG4 |
| 廠商： | Texas Instruments |
| 文件頁數(shù)： | 15/28頁 |
| 文件大?。?/td> | 881K |
| 描述： | IC TEMP SENSOR DGTL OUT 8-MSOP |
| 標(biāo)準(zhǔn)包裝： | 250 |
| 功能： | 溫度監(jiān)控系統(tǒng)（傳感器） |
| 傳感器類型： | 內(nèi)部和外部 |
| 感應(yīng)溫度： | -40°C ~ 125°C |
| 精確度： | ±3°C 本地（最大），±5°C 遠(yuǎn)程（最大） |
| 拓?fù)洌?/td> | ADC，比較器，寄存器庫 |
| 輸出類型： | 2 線 SMBus? |
| 輸出警報(bào)： | 是 |
| 輸出風(fēng)扇： | 是 |
| 電源電壓： | 3 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-TSSOP，8-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-MSOP |
| 包裝： | 帶卷 (TR) |
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TMP401
SBOS371A AUGUST 2006 REVISED OCTOBER 2007
www.ti.com
15
BUS OVERVIEW
The TMP401 is SMBus interface-compatible. In SMBus
protocol, the device that initiates the transfer is called a
master, and the devices controlled by the master are
slaves. The bus must be controlled by a master device that
generates the serial clock (SCL), controls the bus access,
and generates the START and STOP conditions.
To address a specific device, a START condition is
initiated. START is indicated by pulling the data line (SDA)
from a high to low logic level while SCL is high. All slaves
on the bus shift in the slave address byte, with the last bit
indicating whether a read or write operation is intended.
During the ninth clock pulse, the slave being addressed
responds to the master by generating an Acknowledge
and pulling SDA low.
Data transfer is then initiated and sent over eight clock
pulses followed by an Acknowledge bit. During data
transfer SDA must remain stable while SCL is high,
because any change in SDA while SCL is high is
interpreted as a control signal.
Once all data has been transferred, the master generates
a STOP condition. STOP is indicated by pulling SDA from
low to high, while SCL is high.
SERIAL INTERFACE
The TMP401 operates only as a slave device on either the
Two-Wire bus or the SMBus. Connections to either bus are
made via the open-drain I/O lines, SDA and SCL. The SDA
and SCL pins feature integrated spike suppression filters
and Schmitt triggers to minimize the effects of input spikes
and bus noise. The TMP401 supports the transmission
protocol for fast (1kHz to 400kHz) and high-speed (1kHz
to 3.4MHz) modes. All data bytes are transmitted MSB
first.
SERIAL BUS ADDRESS
To communicate with the TMP401, the master must first
address slave devices via a slave address byte. The slave
address byte consists of seven address bits, and a
direction bit indicating the intent of executing a read or
write operation. The address of the TMP401 is 4Ch
(1001100b).
READ/WRITE OPERATIONS
Accessing a particular register on the TMP401 is
accomplished by writing the appropriate value to the
Pointer Register. The value for the Pointer Register is the
first byte transferred after the slave address byte with the
R/W
bit low. Every write operation to the TMP401 requires
a value for the Pointer Register (see Figure 14).
When reading from the TMP401, the last value stored in
the Pointer Register by a write operation is used to
determine which register is read by a read operation. To
change the register pointer for a read operation, a new
value must be written to the Pointer Register. This
transaction is accomplished by issuing a slave address
byte with the R/W
bit low, followed by the Pointer Register
byte. No additional data is required. The master can then
generate a START condition and send the slave address
byte with the R/W
bit high to initiate the read command.
See Figure 15 for details of this sequence. If repeated
reads from the same register are desired, it is not
necessary to continually send the Pointer Register bytes,
because the TMP401 retains the Pointer Register value
until it is changed by the next write operation. Note that
register bytes are sent MSB first, followed by the LSB.
TIMING DIAGRAMS
The TMP401 is Two-Wire and SMBus compatible.
Figure 13 to Figure 16 describe the various operations on
the TMP401. Bus definitions are given below. Parameters
for Figure 13 are defined in Table 11.
Bus Idle: Both SDA and SCL lines remain high.
Start Data Transfer: A change in the state of the SDA line,
from high to low, while the SCL line is high, defines a
START condition. Each data transfer is initiated with a
START condition.
Stop Data Transfer: A change in the state of the SDA line
from low to high while the SCL line is high defines a STOP
condition. Each data transfer terminates with a repeated
START or STOP condition.
Data Transfer: The number of data bytes transferred
between a START and a STOP condition is not limited and
is determined by the master device. The receiver
acknowledges the transfer of data.
Acknowledge: Each receiving device, when addressed,
is obliged to generate an Acknowledge bit. A device that
acknowledges must pull down the SDA line during the
Acknowledge clock pulse in such a way that the SDA line
is stable low during the high period of the Acknowledge
clock pulse. Setup and hold times must be taken into
account. On a master receive, data transfer termination
can be signaled by the master generating a
Not-Acknowledge on the last byte that has been
transmitted by the slave.
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